Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : dti_flop_asyn_soffa_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
66.67 66.67

Source File(s) :
/nfs_project/gemini/DV/nadeem/dv/main_reg_14_10_2022/main_reg_excl_ddr_puff_14_10_2022/gemini/design/mem_ss/ddr_ss/../../ip/dti/libs/dti_tm16_phy/hdl/library/dti_tm16ffc_16f96_9t_stdcells_rev1p0p0_pwr.v

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst37.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst38.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst39.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst51.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst53.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst56.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst60.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst61.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst65.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst71.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst78.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst84.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst85.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst88.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst97.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst101.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst104.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst138.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst139.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst144.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst152.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst153.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst155.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst163.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst169.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst173.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst176.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst190.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst193.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst201.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst205.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst206.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst207.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst210.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst213.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst216.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst219.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst240.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst241.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst242.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst247.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst253.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst262.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst277.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst285.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst290.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst292.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst296.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst298.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst309.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst323.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst326.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst336.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst354.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst364.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst366.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst368.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst369.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst386.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst405.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst410.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst414.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst417.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst420.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst421.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst428.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst429.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst430.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst431.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst445.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst452.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst460.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst461.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst471.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst477.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst491.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst492.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst498.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst505.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst507.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst522.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst541.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst543.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst554.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst564.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst565.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst575.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst577.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst581.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst582.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst584.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst585.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst588.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst591.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst604.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst605.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst613.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst631.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst640.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst642.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst644.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst655.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst656.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst658.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst677.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst687.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst692.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst694.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst696.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst702.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst707.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst720.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst724.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst742.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst746.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst748.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst753.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst761.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst762.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst765.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst768.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst771.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst774.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst778.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst789.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst792.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst798.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst801.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst807.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst809.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst810.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst811.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst825.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst827.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst829.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst836.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst848.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst854.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst855.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst856.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst861.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst866.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst876.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst877.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst878.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst881.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst890.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst891.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst893.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst896.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst900.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst906.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst907.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst918.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst935.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst939.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst942.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst946.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst948.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst949.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst956.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst960.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst963.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst966.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst978.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst982.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst983.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst989.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst992.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1008.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1025.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1028.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1034.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1042.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1043.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1045.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1047.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1057.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1060.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1065.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1067.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1083.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1089.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1094.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1100.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1115.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1119.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1130.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1133.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1145.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1148.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1149.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1154.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1169.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1174.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1177.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1179.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1185.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1201.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1202.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1203.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1214.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1218.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1224.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1233.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1234.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1235.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1241.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1249.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1283.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1288.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1297.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1298.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1307.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1309.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1313.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1336.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1342.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1348.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1357.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1364.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1365.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1366.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1371.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1376.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1378.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1386.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1393.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1394.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1402.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1408.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1412.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1441.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1446.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1449.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1450.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1456.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1457.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1458.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1467.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1479.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1494.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1496.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1511.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1515.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1518.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1519.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1522.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1531.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1561.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1564.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1566.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1571.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1574.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1577.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1582.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1585.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1593.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1597.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1600.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1604.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1617.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1622.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1626.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1632.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1633.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1636.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1647.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1652.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1655.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1657.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1672.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1673.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1678.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1681.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1696.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1704.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1709.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1712.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1716.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1725.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1731.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1734.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1738.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1739.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1742.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1752.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1756.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1759.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1771.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1775.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1782.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1785.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1788.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1789.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1795.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1798.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1803.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1826.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1828.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1835.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1837.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1839.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1848.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1854.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1859.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1863.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1868.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1872.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1877.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1885.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1887.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1889.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1896.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1897.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1900.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1903.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1926.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1928.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1944.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1949.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1959.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1964.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1966.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1968.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1982.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1984.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1989.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1992.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1995.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1997.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1999.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2000.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2019.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2026.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2027.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2028.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2032.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2035.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2045.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2050.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2051.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2052.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2057.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2060.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2064.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2065.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2088.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2101.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2108.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2113.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2115.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2116.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2123.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2128.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2145.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2147.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2149.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2165.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2185.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2201.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2205.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2209.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2214.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2217.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2224.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2245.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2257.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2260.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2261.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2267.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2270.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2278.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2279.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2299.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2300.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2304.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2308.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2310.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2322.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2335.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2342.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2343.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2345.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2358.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2370.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2388.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2390.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2393.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2396.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2397.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2398.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2412.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2416.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2428.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2439.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2440.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2445.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2452.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2459.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2460.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2465.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2467.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2473.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2483.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2486.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2491.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2492.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2496.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2498.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2499.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2507.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2512.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2515.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2520.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2522.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2527.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2529.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2539.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2546.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2548.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2550.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2558.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2563.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2588.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2597.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2606.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2612.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2616.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2621.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2625.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2626.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2627.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2633.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2639.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2640.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2643.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2660.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2673.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2679.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2690.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2692.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2719.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2727.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2734.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2743.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2747.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2770.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2777.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2784.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2785.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2788.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2797.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2803.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2806.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2808.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2810.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2817.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2822.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2833.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2846.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2853.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2857.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2858.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2866.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2878.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2879.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2887.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2893.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2894.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2896.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2898.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2899.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2903.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2905.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2907.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2908.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2909.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2918.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2920.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2922.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2924.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2932.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2946.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2955.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2959.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2972.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2973.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2983.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2984.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2987.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2988.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2997.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3000.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3002.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3005.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3007.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3009.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3012.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3028.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3033.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3039.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3051.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3053.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3054.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3056.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3059.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3076.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3085.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3092.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3098.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3101.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3102.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3114.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3117.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3118.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3119.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3121.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3125.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3137.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3141.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3149.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3152.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3166.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3171.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3172.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3180.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3192.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3202.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3205.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3208.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3218.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3220.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3221.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3222.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3223.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3227.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3228.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3237.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3245.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3251.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3252.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3256.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3261.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3262.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3272.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3274.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3278.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3289.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3290.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3298.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3304.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3354.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3355.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3359.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3366.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3368.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3373.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3379.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3384.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3387.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3400.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3405.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3407.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3408.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3412.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3417.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3420.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3425.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3430.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3438.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3441.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3444.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3450.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3457.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3467.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3468.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3472.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3473.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3475.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3479.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3485.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3495.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3499.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3502.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3504.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3507.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3516.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3520.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3525.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3538.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3540.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3542.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3551.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3561.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3570.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3575.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3578.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3588.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3596.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3606.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3608.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3610.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3614.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3615.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3620.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3640.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3641.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3646.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3650.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3659.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3662.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3675.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3677.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3688.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3700.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3713.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3716.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3723.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3725.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3727.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3728.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3731.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3735.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3755.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3761.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3763.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3765.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3767.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3771.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3774.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3778.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3799.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3807.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3823.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3827.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3830.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3835.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3838.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3842.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3846.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3854.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3864.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3866.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3868.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3873.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3882.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3886.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3897.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3901.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3904.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3913.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3931.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3940.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3958.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3966.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3970.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3971.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3990.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3997.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4005.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4006.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4008.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4014.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4019.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4020.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4028.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4031.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4032.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4034.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4037.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4051.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4060.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4073.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4074.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4078.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4083.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4094.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4109.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4114.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4117.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4123.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4147.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4173.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4178.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4180.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4187.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4189.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4196.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4199.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4205.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4211.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4212.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4214.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4222.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4224.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4231.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4235.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4236.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4239.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4242.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4252.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4256.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4257.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4258.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4262.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4265.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4271.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4274.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4276.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4278.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4285.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4287.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4289.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4290.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4296.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4300.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4320.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4331.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4366.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4368.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4376.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4382.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4385.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4393.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4395.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4398.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4405.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4406.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4408.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4411.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4414.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4415.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4416.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4427.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4429.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4444.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4445.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4448.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4457.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4458.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4473.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4474.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4482.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4484.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4485.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4496.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4498.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4501.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4525.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4533.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4556.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4559.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4562.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4571.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4578.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4582.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4599.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4604.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4611.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4613.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4617.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4618.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4629.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4631.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4639.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4647.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4649.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4653.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4658.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4659.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4662.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4667.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4668.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4673.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4684.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4692.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4709.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4710.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4711.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4715.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4717.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4719.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4720.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4725.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4726.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4731.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4734.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4754.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4758.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4763.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4765.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4769.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4790.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4791.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4801.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4809.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4817.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4819.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4830.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4836.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4837.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4855.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4857.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4858.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4862.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4863.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4865.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4869.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4880.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4882.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4903.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4906.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4907.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4911.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4914.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4924.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4927.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4933.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4934.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4947.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4948.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4953.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4954.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4956.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4960.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4963.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4966.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4967.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4968.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4971.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4975.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4979.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4984.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4989.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4995.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5008.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5015.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5016.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5031.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5034.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5039.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5045.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5051.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5057.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5059.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5064.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5073.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5088.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5090.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5091.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5092.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5105.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5106.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5108.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5118.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5120.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5128.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5150.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5173.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5182.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5183.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5189.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5199.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5202.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5210.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5211.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5213.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5232.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5234.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5238.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5246.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5251.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5254.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5259.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5264.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5267.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5269.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5271.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5279.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5281.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5285.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5287.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5293.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5313.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5317.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5329.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5331.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5335.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5338.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5339.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5342.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5346.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5347.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5351.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5357.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5364.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5366.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5394.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5401.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5405.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5420.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5425.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5440.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5447.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5455.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5456.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5461.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5462.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5464.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5469.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5472.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5475.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5478.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5480.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5485.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5486.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5487.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5493.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5519.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5529.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5533.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5546.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5565.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5571.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5581.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5583.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5594.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5598.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5602.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5614.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5615.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5632.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5633.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5634.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5638.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5643.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5644.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5645.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5647.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5650.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5660.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5664.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5675.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5680.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5682.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5687.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5688.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5692.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5699.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5710.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5715.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5718.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5724.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5730.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5731.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5733.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5734.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5742.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5757.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5762.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5769.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5774.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5781.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5786.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5796.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5803.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5804.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5809.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5810.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5814.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5819.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5820.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5821.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5836.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5837.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5847.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5850.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5871.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5872.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5878.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5888.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5892.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5896.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5905.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5906.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5920.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5923.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5925.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5940.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5943.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5955.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5965.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5970.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5971.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5972.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5975.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5978.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5984.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5987.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5988.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5989.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5990.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5992.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6011.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6016.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6017.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6018.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6028.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6034.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6047.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6049.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6050.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6055.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6064.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6073.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6077.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6083.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6090.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6095.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6102.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6116.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6123.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6126.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6141.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6144.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6156.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6163.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6169.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6176.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6177.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6179.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6188.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6189.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6197.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6198.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6201.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6212.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6215.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6216.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6221.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6226.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6236.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6240.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6244.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6252.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6260.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6270.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6271.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6276.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6277.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6283.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6284.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6285.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6286.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6292.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6299.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6302.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6305.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6330.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6334.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6342.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6353.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6364.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6376.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6382.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6383.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6389.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6408.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6414.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6416.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6417.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6438.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6444.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6446.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6461.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6465.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6466.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6468.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6470.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6484.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6487.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6494.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6495.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6527.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6537.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6538.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6539.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6545.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6547.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6548.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6551.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6557.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6559.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6568.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6569.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6570.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6578.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6580.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6583.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6586.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6597.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6607.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6609.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6611.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6613.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6616.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6622.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6625.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6630.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6631.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6641.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6643.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6649.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6650.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6653.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6655.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6659.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6666.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6667.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6677.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6678.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6685.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6692.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6710.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6714.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6718.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6719.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6728.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6740.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6744.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6745.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6747.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6748.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6753.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6755.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6759.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6762.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6766.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6771.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6774.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6776.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6780.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6785.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6791.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6803.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6804.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6807.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6828.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6833.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6835.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6840.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6872.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6873.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6878.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6881.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6883.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6895.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6899.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6918.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6924.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6933.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6937.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6939.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6940.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6942.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6943.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6945.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6946.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6958.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6970.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6972.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6976.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6977.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6982.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6985.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6986.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6990.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6996.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7006.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7016.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7028.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7033.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7037.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7038.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7039.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7040.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7052.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7061.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7075.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7079.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7081.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7090.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7091.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7092.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7097.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7107.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7122.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7137.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7138.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7153.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7170.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7174.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7175.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7177.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7188.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7198.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7205.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7206.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7213.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7215.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7221.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7227.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7232.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7254.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7257.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7263.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7265.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7268.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7275.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7278.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7289.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7291.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7292.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7293.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7318.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7319.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7323.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7326.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7328.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7334.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7351.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7364.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7368.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7376.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7380.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7384.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7388.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7389.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7394.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7398.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7405.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7411.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7418.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7424.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7429.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7433.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7444.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7450.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7455.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7461.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7462.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7465.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7466.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7468.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7473.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7475.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7476.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7492.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7496.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7513.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7526.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7534.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7537.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7544.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7549.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7556.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7561.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7565.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7571.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7575.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7591.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7596.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7597.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7613.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7617.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7625.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7626.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7630.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7639.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7642.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7650.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7663.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7669.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7673.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7679.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7681.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7685.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7695.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7697.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7705.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7708.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7712.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7725.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7730.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7735.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7743.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7749.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7752.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7754.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7756.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7758.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7759.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7768.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7784.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7791.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7793.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7800.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7812.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7825.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7834.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7840.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7843.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7865.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7878.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7894.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7897.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7903.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7904.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7905.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7914.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7920.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7922.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7941.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7963.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7964.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7971.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7976.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7977.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7986.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7994.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7998.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8006.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8011.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8012.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8015.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8018.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8023.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8024.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8025.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8027.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8029.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8038.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8042.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8044.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8055.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8058.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8066.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8068.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8076.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8083.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8087.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8089.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8092.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8095.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8100.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8105.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8117.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8122.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8126.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8127.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8131.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8136.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8154.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8156.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8157.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8160.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8165.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8166.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8167.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8168.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8187.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8188.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8203.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8209.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8217.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8222.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8225.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8230.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8233.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8234.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8235.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8239.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8241.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8252.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8254.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8257.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8269.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8274.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8277.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8281.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8283.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8289.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8292.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8293.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8302.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8306.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8315.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8330.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8333.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8347.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8348.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8369.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8379.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8386.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8389.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8391.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8407.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8410.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8418.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8428.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8429.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8442.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8446.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8452.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8456.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8460.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8462.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8470.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8474.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8479.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8482.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8483.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8489.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8490.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8495.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8531.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8535.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8541.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8545.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8548.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8554.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8556.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8557.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8563.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8566.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8567.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8570.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8577.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8579.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8581.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8596.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8605.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8612.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8618.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8619.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8627.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8635.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8640.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8649.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8668.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8685.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8687.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8690.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8705.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8708.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8715.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8721.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8722.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8730.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8733.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8744.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8746.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8751.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8752.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8754.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8756.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8770.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8774.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8781.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8785.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8788.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8789.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8792.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8798.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8800.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8805.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8806.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8808.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8809.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8812.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8818.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8847.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8848.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8855.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8858.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8864.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8872.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8883.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8885.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8889.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8896.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8898.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8907.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8911.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8926.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8927.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8928.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8933.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8939.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8947.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8954.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8956.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8962.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8965.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8967.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8971.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8975.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8976.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8986.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8988.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8993.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8999.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9001.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9002.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9005.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9009.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9012.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9020.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9025.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9035.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9039.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9049.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9052.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9054.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9060.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9067.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9073.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9084.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9086.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9095.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9106.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9110.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9114.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9125.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9127.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9156.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9159.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9162.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9169.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9170.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9173.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9181.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9188.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9189.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9192.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9193.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9201.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9205.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9211.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9237.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9239.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9242.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9263.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9265.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9269.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9270.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9273.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9275.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9278.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9283.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9300.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9334.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9335.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9340.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9343.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9347.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9349.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9355.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9372.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9376.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9380.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9416.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9418.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9419.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9420.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9421.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9425.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9426.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9430.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9442.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9452.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9455.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9461.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9468.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9477.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9489.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9490.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9494.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9498.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9502.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9514.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9519.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9526.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9529.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9538.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9542.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9547.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9549.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9558.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9559.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9564.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9576.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9577.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9581.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9589.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9590.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9593.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9596.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9599.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9604.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9616.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9617.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9630.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9633.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9638.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9642.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9657.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9658.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9667.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9693.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9697.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9721.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9724.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9726.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9729.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9735.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9739.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9746.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9752.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9766.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9786.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9796.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9797.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9801.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9803.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9806.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9807.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9809.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9826.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9839.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9841.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9843.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9856.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9857.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9865.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9866.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9868.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9875.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9877.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9880.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9896.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9898.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9899.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9918.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9928.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9930.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9932.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9934.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9939.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9943.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9946.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9953.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9972.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9976.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9981.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9982.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9985.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9987.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10008.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10015.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10017.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10022.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10030.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10031.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10034.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10036.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10039.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10040.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10053.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10054.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10056.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10060.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10065.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10066.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10068.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10075.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10077.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10078.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10085.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10089.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10090.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10095.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10112.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10122.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10129.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10133.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10138.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10144.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10146.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10156.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10158.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10160.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10170.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10171.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10178.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10185.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10190.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10194.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10200.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10201.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10203.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10206.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10217.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10224.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10226.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10246.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10266.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10273.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10274.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10289.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10304.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10307.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10323.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10324.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10330.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10340.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10341.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10344.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10345.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10350.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10352.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10358.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10360.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10361.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10365.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10368.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10378.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10383.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10387.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10391.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10405.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10410.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10411.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10416.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10421.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10423.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10438.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10443.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10444.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10451.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10453.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10455.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10457.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10459.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10466.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10467.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10468.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10484.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10489.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10490.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10499.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10501.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10502.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10509.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10512.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10513.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10515.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10521.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10522.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10527.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10530.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10539.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10557.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10561.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10569.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10573.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10592.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10595.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10597.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10606.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10607.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10635.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10652.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10659.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10683.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10684.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10689.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10694.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10699.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10700.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10701.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10710.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10715.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10732.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10740.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10741.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10743.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10754.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10762.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10766.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10772.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10777.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10784.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10796.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10809.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10814.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10822.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10827.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10830.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10831.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10833.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10837.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10840.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10846.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10853.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10854.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10860.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10861.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10870.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10871.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10877.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10878.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10890.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10903.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10915.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10917.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10920.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10922.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10925.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10931.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10945.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10947.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10948.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10953.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10957.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10968.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10969.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10980.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10987.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10991.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10995.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10997.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10998.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10999.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11001.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11019.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11020.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11029.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11038.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11060.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11068.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11072.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11078.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11081.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11088.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11095.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11098.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11110.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11112.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11128.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11129.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11138.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11145.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11155.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11160.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11170.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11171.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11172.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11174.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11185.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11187.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11202.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11204.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11205.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11214.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11217.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11221.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11227.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11229.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11247.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11249.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11257.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11260.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11268.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11270.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11277.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11297.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11304.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11306.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11312.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11319.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11324.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11335.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11343.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11347.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11351.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11356.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11359.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11368.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11375.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11378.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11388.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11399.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11403.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11422.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11425.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11429.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11430.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11431.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11432.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11433.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11436.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11438.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11446.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11455.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11466.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11468.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11479.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11489.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11490.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11491.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11494.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11498.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11501.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11502.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11504.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11519.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11524.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11525.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11543.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11564.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11566.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11592.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11607.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11609.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11613.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11619.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11620.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11627.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11629.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11631.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11634.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11637.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11639.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11643.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11650.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11652.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11663.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11672.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11673.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11678.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11683.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11685.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11693.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11705.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11709.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11720.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11727.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11731.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11737.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11750.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11760.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11769.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11793.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11794.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11801.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11807.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11827.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11833.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11837.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11840.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11841.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11845.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11860.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11862.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11869.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11875.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11877.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11878.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11883.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11895.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11902.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11915.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11918.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11921.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11922.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11924.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11925.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11941.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11942.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11947.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11948.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11958.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11959.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11962.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11973.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11975.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11983.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11993.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12003.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12004.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12005.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12011.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12022.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12025.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12035.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12049.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12056.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12060.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12073.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12078.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12082.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12084.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12086.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12089.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12100.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12101.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12102.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12112.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12127.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12129.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12132.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12136.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12138.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12141.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12142.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12143.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12148.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12152.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12168.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12170.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12173.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12174.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12176.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12185.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12208.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12210.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12214.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12221.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12229.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12230.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12234.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12236.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12241.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12247.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12252.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12253.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12262.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12267.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12283.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12285.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12287.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12293.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12295.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12296.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12302.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12310.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12319.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12328.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12330.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12331.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12334.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12336.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12343.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12347.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12353.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12361.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12364.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12365.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12385.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12390.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12401.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12431.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12433.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12445.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12447.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12458.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12464.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12465.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12471.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12477.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12480.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12482.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12487.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12496.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12498.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12499.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12501.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12502.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12506.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12508.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12530.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12531.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12553.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12560.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12562.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12565.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12570.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12573.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12575.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12581.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12585.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12590.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12598.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12614.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12617.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12621.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12622.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12636.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12642.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12643.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12648.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12653.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12654.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12659.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12660.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12666.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12668.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12669.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12674.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12689.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12696.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12704.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12707.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12710.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12715.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12725.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12727.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12755.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12759.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12761.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12787.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12793.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12800.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12815.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12824.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12830.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12832.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12837.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12850.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12853.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12855.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12857.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12868.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12871.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12877.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12880.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12891.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12895.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12896.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12897.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12899.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12900.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12902.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12905.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12908.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12914.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12918.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12924.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12926.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12928.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12931.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12938.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12939.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12941.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12954.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12958.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12962.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12964.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12970.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12979.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12987.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12991.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12992.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12994.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12995.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12998.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13008.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13012.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13016.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13017.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13023.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13031.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13038.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13050.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13052.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13055.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13064.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13094.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13095.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13114.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13115.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13122.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13143.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13154.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13155.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13158.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13166.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13172.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13177.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13183.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13188.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13193.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13210.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13215.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13224.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13225.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13231.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13241.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13242.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13251.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13259.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13260.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13263.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13264.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13277.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13282.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13288.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13293.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13298.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13299.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13301.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13303.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13304.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13305.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13308.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13312.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13334.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13342.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13359.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13360.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13362.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13377.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13379.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13381.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13385.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13387.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13390.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13393.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13399.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13400.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13402.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13404.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13416.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13431.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13432.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13442.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13452.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13465.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13466.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13486.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13489.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13494.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13503.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13512.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13516.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13524.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13527.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13536.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13538.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13546.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13549.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13556.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13558.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13562.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13564.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13577.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13579.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13581.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13591.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13599.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13604.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13611.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13612.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13614.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13616.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13630.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13634.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13635.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13640.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13650.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13659.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13660.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13664.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13667.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13668.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13669.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13676.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13684.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13690.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13692.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13707.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13713.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13715.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13724.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13733.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13736.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13744.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13756.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13766.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13781.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13782.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13791.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13792.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13799.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13802.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13803.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13812.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13827.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13828.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13832.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13837.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13838.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13839.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13845.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13849.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13859.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13865.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13866.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13870.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13877.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13878.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13879.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13881.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13897.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13900.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13914.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13917.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13920.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13922.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13925.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13931.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13942.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13954.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13959.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13964.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13965.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13967.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13977.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13988.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13993.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13996.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14000.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14009.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14021.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14034.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14038.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14042.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14044.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14047.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14048.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14050.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14055.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14075.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14076.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14087.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14089.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14091.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14094.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14097.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14098.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14105.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14106.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14118.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14121.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14123.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14125.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14126.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14131.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14135.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14138.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14141.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14162.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14178.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14179.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14186.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14192.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14199.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14216.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14223.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14228.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14236.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14245.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14251.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14263.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14270.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14278.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14289.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14305.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14312.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14322.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14324.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14333.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14341.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14342.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14343.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14348.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14358.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14359.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14368.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14376.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14382.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14383.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14385.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14386.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14393.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14395.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14403.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14409.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14410.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14411.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14412.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14414.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14420.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14421.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14422.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14427.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14429.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14435.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14436.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14438.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14442.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14444.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14455.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14462.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14483.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14498.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14506.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14518.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14525.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14533.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14545.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14546.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14559.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14578.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14579.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14580.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14582.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14584.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14587.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14591.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14603.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14605.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14606.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14616.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14620.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14622.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14627.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14640.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14658.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14661.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14665.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14668.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14672.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14673.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14681.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14695.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14696.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14697.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14698.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14700.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14713.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14720.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14725.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14726.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14732.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14737.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14745.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14750.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14751.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14753.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14759.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14772.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14776.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14781.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14788.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14794.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14806.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14807.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14820.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14828.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14830.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14838.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14847.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14851.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14862.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14867.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14869.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14873.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14878.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14879.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14882.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14885.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14895.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14902.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14904.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14909.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14913.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14914.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14922.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14924.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14925.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14927.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14933.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14939.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14941.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14960.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14977.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14983.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14986.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14988.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14995.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14999.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15012.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15014.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15019.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15025.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15030.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15034.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15050.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15073.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15082.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15086.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15088.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15089.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15092.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15097.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15098.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15101.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15104.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15109.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15115.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15127.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15148.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15151.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15153.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15160.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15172.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15181.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15183.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15187.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15193.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15198.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15203.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15225.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15238.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15241.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15252.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15253.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15266.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15269.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15282.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15290.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15304.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15306.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15312.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15315.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15320.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15332.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15334.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15340.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15343.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15349.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15353.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15354.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15357.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15360.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15363.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15364.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15369.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15375.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15376.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15377.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15385.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15404.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15412.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15413.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15424.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15444.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15448.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15457.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15459.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15465.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15466.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15467.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15470.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15476.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15477.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15486.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15488.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15489.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15496.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15499.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15501.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15510.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15511.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15541.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15547.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15549.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15554.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15558.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15569.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15584.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15588.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15590.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15595.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15597.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15610.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15611.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15613.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15614.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15615.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15623.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15629.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15635.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15636.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15641.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15653.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15660.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15665.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15666.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15678.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15681.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15696.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15700.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15701.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15709.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15715.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15716.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15720.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15722.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15724.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15728.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15731.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15742.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15750.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15753.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15759.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15766.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15767.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15774.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15781.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15785.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15792.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15799.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15817.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15819.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15862.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15863.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15864.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15867.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15873.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15877.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15879.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15883.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15887.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15889.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15893.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15903.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15908.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15913.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15914.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15917.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15922.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15923.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15924.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15933.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15937.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15939.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15940.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15959.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15962.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15971.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15982.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15986.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15987.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15989.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15991.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15992.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15994.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16013.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16020.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16040.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16054.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16056.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16061.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16063.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16073.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16076.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16087.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16113.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16115.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16119.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16132.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16133.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16136.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16140.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16143.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16158.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16160.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16161.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16162.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16163.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16166.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16181.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16190.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16195.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16198.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16199.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16203.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16204.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16207.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16213.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16221.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16222.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16224.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16235.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16237.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16252.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16255.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16256.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16265.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16267.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16270.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16271.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16275.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16283.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16290.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16294.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16310.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16313.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16316.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16323.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16324.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16333.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16336.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16344.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16357.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16358.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16363.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16365.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16369.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16376.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16385.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16387.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16391.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16393.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16394.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16403.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16405.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16412.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16457.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16459.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16472.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16490.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16509.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16524.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16540.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16546.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16548.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16549.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16563.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16564.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16566.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16567.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16570.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16575.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16580.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16611.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16614.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16633.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16635.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16637.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16638.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16647.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16657.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16658.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16660.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16674.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16678.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16682.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16683.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16691.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16701.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16710.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16734.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16736.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16739.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16746.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16748.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16750.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16757.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16767.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16773.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16776.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16780.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16790.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16796.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16805.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16810.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16814.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16823.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16832.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16846.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16848.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16858.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16861.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16869.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16877.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16878.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16885.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16899.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16909.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16920.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16925.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16933.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16935.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16939.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16945.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16951.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16953.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16963.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16967.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16974.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16978.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16992.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17001.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17004.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17008.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17018.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17029.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17032.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17050.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17054.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17056.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17068.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17071.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17078.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17081.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17089.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17091.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17098.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17102.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17103.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17108.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17113.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17115.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17119.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17129.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17135.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17144.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17170.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17173.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17174.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17179.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17180.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17182.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17184.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17185.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17186.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17190.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17192.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17219.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17224.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17226.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17230.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17241.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17247.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17257.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17260.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17264.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17265.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17270.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17277.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17278.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17293.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17300.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17301.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17322.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17336.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17341.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17343.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17346.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17352.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17353.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17354.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17363.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17374.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17380.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17387.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17401.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17409.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17414.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17423.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17432.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17435.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17448.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17474.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17480.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17482.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17488.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17491.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17494.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17521.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17528.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17533.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17534.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17538.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17545.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17555.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17561.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17574.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17584.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17598.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17599.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17610.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17617.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17630.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17637.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17643.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17651.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17655.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17665.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17666.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17674.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17683.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17693.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17700.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17722.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17724.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17729.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17731.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17767.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17769.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17776.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17781.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17786.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17797.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17802.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17812.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17814.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17815.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17820.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17835.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17850.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17855.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17857.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17858.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17860.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17869.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17876.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17881.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17887.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17897.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17899.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17900.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17904.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17917.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17931.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17932.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17960.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17962.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17964.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17969.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17972.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17974.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17984.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17989.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17990.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17991.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18000.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18003.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18004.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18012.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18017.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18019.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18020.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18021.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18030.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18039.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18044.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18045.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18047.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18048.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18050.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18052.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18055.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18058.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18063.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18064.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18073.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18074.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18075.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18081.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18082.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18085.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18088.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18095.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18096.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18097.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18100.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18101.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18103.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18104.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18109.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18111.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18112.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18128.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18129.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18156.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18158.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18187.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18189.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18206.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18208.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18211.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18216.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18217.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18220.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18228.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18231.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18246.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18247.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18254.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18266.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18267.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18270.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18294.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18305.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18311.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18313.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18314.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18317.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18337.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18357.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18359.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18361.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18364.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18369.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18388.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18394.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18407.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18409.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18415.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18421.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18423.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18426.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18427.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18429.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18430.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18435.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18442.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18446.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18451.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18453.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18454.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18456.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18459.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18460.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18464.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18468.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18472.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18475.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18478.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18482.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18488.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18496.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18501.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18502.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18504.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18510.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18513.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18516.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18527.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18537.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18541.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18550.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18552.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18563.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18570.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18571.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18572.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18575.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18580.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18581.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18592.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18603.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18605.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18616.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18618.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18622.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18632.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18650.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18674.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18678.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18685.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18714.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18720.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18725.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18728.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18739.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18742.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18749.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18755.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18759.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18766.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18767.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18768.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18769.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18770.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18773.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18774.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18776.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18781.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18794.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18797.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18807.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18808.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18815.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18827.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18830.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18846.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18848.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18852.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18868.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18870.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18873.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18878.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18880.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18895.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18896.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18899.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18901.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18905.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18911.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18913.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18916.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18920.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18922.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18932.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18934.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18952.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18978.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18981.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18986.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18990.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18993.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19015.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19021.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19047.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19049.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19072.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19077.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19081.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19086.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19089.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19091.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19099.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19100.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19105.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19106.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19109.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19135.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19142.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19155.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19165.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19175.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19182.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19188.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19191.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19196.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19199.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19210.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19214.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19216.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19218.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19222.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19223.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19224.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19225.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19232.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19239.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19240.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19241.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19248.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19261.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19279.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19285.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19290.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19291.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19308.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19326.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19361.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19364.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19365.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19369.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19370.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19372.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19376.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19377.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19383.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19405.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19413.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19426.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19430.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19432.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19452.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19455.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19459.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19461.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19462.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19467.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19470.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19474.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19479.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19486.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19493.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19497.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19501.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19507.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19513.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19522.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19526.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19528.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19531.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19532.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19536.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19549.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19555.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19560.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19562.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19563.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19569.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19570.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19577.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19586.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19589.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19599.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19609.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19612.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19615.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19618.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19624.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19629.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19633.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19636.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19667.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19675.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19676.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19687.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19689.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19694.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19696.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19699.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19703.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19705.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19709.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19713.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19716.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19720.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19724.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19727.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19736.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19737.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19750.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19761.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19765.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19771.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19772.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19784.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19785.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19790.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19797.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19800.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19810.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19813.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19818.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19831.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19837.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19843.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19848.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19851.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19864.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19867.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19869.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19876.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19890.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19899.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19908.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19909.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19914.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19917.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19925.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19930.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19935.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19941.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19952.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19958.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19959.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19960.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19963.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19967.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19974.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19977.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19982.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19996.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20004.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20008.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20019.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20021.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20026.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20028.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20049.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20050.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20058.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20061.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20063.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20075.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20088.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20093.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20095.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20096.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20097.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20106.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20119.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20124.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20132.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20136.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20147.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20154.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20155.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20157.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20158.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20159.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20164.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20174.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20178.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20180.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20193.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20196.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20198.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20200.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20209.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20218.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20226.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20227.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20232.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20245.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20272.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20287.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20293.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20295.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20296.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20298.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20300.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20304.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20310.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20312.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20314.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20325.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20326.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20329.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20355.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20374.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20385.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20393.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20401.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20402.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20406.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20419.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20432.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20433.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20440.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20441.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20456.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20466.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20476.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20477.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20480.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20483.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20500.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20504.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20505.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20507.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20508.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20512.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20516.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20523.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20524.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20525.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20528.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20538.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20541.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20558.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20561.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20564.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20581.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20584.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20606.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20613.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20629.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20632.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20638.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20640.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20641.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20642.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20645.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20646.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20651.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20664.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20665.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20670.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20672.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20675.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20677.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20678.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20683.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20696.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20697.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20712.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20717.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20728.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20730.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20741.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20744.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20747.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20752.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20754.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20761.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20771.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20772.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20776.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20778.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20787.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20788.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20794.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20814.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20816.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20818.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20823.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20828.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20830.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20831.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20837.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20843.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20850.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20858.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20859.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20862.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20863.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20864.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20865.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20889.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20902.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20905.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20907.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20924.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20929.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20930.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20940.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20947.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20950.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20954.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20955.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20958.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20962.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20965.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20968.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20980.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20994.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21002.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21003.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21006.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21017.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21019.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21027.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21029.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21036.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21042.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21061.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21065.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21074.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21077.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21083.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21085.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21094.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21098.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21110.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21112.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21140.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21142.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21143.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21147.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21155.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21188.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21193.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21200.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21213.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21214.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21223.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21225.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21227.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21228.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21230.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21231.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21240.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21242.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21252.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21253.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21259.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21264.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21280.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21287.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21288.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21293.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21302.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21310.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21319.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21323.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21338.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21347.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21348.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21350.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21365.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21372.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21374.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21376.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21380.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21385.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21386.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21388.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21393.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21398.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21400.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21412.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21416.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21417.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21419.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21423.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21430.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21432.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21436.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21438.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21444.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21452.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21455.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21460.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21463.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21474.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21478.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21485.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21494.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21499.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21507.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21511.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21523.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21524.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21529.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21535.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21544.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21546.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21558.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21560.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21562.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21572.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21574.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21578.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21580.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21583.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21593.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21594.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21605.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21608.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21623.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21625.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21636.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21652.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21655.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21673.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21694.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21708.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21716.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21720.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21736.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21738.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21741.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21756.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21761.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21762.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21768.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21772.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21791.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21793.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21799.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21803.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21816.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21823.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21824.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21825.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21827.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21862.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21872.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21875.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21885.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21890.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21894.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21902.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21918.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21922.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21929.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21930.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21932.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21938.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21946.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21951.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21952.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21954.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21957.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21958.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21982.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22002.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22012.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22015.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22016.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22023.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22028.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22031.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22040.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22049.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22055.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22067.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22073.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22074.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22077.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22081.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22082.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22083.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22084.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22088.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22090.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22094.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22101.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22105.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22122.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22123.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22127.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22132.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22144.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22149.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22157.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22178.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22186.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22188.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22202.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22210.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22222.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22227.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22229.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22232.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22234.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22237.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22239.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22241.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22248.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22250.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22252.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22253.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22256.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22257.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22264.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22266.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22268.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22269.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22270.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22275.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22278.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22280.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22286.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22288.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22294.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22295.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22302.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22309.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22312.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22314.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22328.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22338.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22342.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22347.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22350.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22354.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22360.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22366.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22368.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22375.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22379.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22385.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22395.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22396.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22406.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22408.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22416.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22419.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22421.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22425.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22429.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22432.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22444.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22446.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22458.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22471.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22474.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22478.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22484.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22491.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22493.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22494.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22495.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22498.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22503.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22506.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22508.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22509.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22515.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22525.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22530.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22549.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22551.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22557.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22560.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22567.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22568.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22573.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22589.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22590.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22609.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22615.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22630.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22634.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22640.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22641.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22644.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22648.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22649.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22659.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22679.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22680.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22682.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22695.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22697.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22700.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22710.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22716.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22719.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22737.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22740.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22745.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22754.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22756.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22761.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22781.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22791.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22794.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22797.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22802.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22804.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22819.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22824.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22835.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22840.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22850.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22851.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22860.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22863.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22876.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22877.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22881.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22882.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22890.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22899.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22901.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22902.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22906.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22915.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22929.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22941.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22951.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22953.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22963.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22965.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22976.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22979.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22980.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22981.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22998.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23003.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23005.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23009.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23011.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23016.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23036.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23038.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23040.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23051.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23063.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23064.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23072.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23077.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23078.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23081.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23082.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23091.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23102.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23109.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23116.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23122.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23138.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23142.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23143.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23160.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23163.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23164.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23172.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23178.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23180.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23190.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23199.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23201.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23203.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23206.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23209.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23215.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23219.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23226.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23228.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23240.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23244.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23249.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23250.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23262.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23274.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23275.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23304.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23316.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23323.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23336.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23342.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23345.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23357.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23358.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23363.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23377.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23389.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23390.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23391.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23398.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23408.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23412.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23413.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23424.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23450.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23453.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23458.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23471.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23475.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23479.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23487.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23490.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23508.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23516.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23522.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23528.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23532.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23534.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23543.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23545.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23561.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23562.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23566.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23580.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23584.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23590.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23593.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23596.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23598.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23617.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23622.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23634.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23635.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23650.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23651.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23660.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23672.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23686.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23690.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23694.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23697.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23699.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23702.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23714.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23719.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23723.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23733.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23746.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23754.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23755.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23771.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23780.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23783.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23786.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23792.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23817.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23818.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23819.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23825.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23835.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23857.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23858.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23862.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23879.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23882.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23883.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23890.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23893.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23898.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23904.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23909.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23911.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23914.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23915.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23917.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23919.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23925.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23928.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23941.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23944.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23952.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23967.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23968.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23972.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23973.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23974.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23981.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23983.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23985.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23994.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23999.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24009.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24010.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24015.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24024.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24025.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24028.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24031.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24041.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24042.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24046.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24048.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24057.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24061.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24065.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24068.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24071.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24074.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24080.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24088.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24089.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24092.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24095.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24097.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24098.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24099.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24101.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24102.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24106.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24112.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24116.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24118.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24125.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24132.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24142.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24152.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24158.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24182.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24194.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24201.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24203.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24205.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24209.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24224.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24225.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24229.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24234.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24235.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24240.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24241.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24245.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24246.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24252.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24260.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24263.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24264.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24267.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24274.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24286.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24288.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24289.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24290.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24297.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24299.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24337.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24339.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24347.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24349.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24354.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24368.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24375.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24378.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24384.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24388.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24390.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24393.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24398.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24405.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24429.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24432.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24446.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24448.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24450.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24451.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24456.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24457.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24465.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24472.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24479.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24492.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24496.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24498.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24507.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24510.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24516.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24522.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24526.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24529.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24533.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24537.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24541.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24542.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24578.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24580.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24582.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24584.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24586.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24592.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24596.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24600.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24606.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24609.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24610.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24612.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24617.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24620.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24622.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24623.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24631.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24633.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24639.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24644.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24645.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24662.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24670.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24672.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24684.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24688.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24690.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24704.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24717.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24718.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24720.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24728.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24745.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24750.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24769.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24773.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24780.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24786.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24788.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24812.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24822.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24828.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24837.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24840.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24845.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24850.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24854.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24855.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24858.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24861.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24866.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24868.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24871.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24874.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24882.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24885.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24890.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24896.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24922.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24924.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24928.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24934.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24936.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24944.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24945.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24954.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24955.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24956.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24968.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24973.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24974.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24975.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24977.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24978.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24990.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24996.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25001.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25004.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25008.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25018.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25024.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25032.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25033.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25036.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25057.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25062.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25067.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25073.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25075.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25078.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25084.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25094.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25105.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25135.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25144.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25151.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25168.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25169.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25175.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25187.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25208.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25209.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25214.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25221.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25225.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25228.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25229.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25234.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25253.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25270.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25271.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25279.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25281.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25290.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25292.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25300.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25307.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25318.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25322.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25325.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25331.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25344.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25350.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25354.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25358.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25359.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25361.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25362.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25363.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25370.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25376.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25377.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25385.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25386.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25393.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25409.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25426.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25429.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25438.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25446.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25449.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25451.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25454.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25456.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25458.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25463.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25469.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25473.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25479.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25483.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25488.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25491.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25503.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25528.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25539.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25540.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25543.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25544.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25551.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25569.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25573.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25574.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25575.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25587.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25594.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25595.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25596.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25603.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25619.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25638.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25643.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25645.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25646.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25647.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25657.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25659.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25663.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25672.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25681.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25692.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25705.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25712.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25713.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25715.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25719.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25723.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25728.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25729.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25736.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25738.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25745.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25754.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25762.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25766.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25769.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25770.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25781.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25786.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25788.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25791.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25797.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25799.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25811.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25813.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25819.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25836.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25839.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25842.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25852.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25853.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25855.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25860.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25865.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25868.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25874.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25875.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25878.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25896.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25897.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25899.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25909.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25921.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25922.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25927.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25930.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25934.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25939.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25944.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25945.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25959.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25965.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25976.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25986.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25991.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25994.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26003.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26012.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26013.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26018.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26021.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26023.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26029.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26032.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26047.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26059.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26063.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26065.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26066.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26068.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26072.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26074.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26087.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26093.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26095.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26100.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26112.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26127.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26139.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26145.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26150.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26151.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26153.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26165.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26169.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26171.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26190.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26192.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26200.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26202.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26218.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26219.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26222.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26228.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26229.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26232.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26237.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26241.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26274.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26283.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26289.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26293.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26320.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26339.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26341.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26346.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26351.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26355.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26361.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26368.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26381.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26392.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26393.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26395.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26402.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26410.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26429.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26433.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26441.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26449.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26453.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26460.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26461.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26464.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26468.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26474.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26476.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26477.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26479.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26483.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26489.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26493.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26494.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26497.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26508.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26509.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26512.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26514.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26521.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26525.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26538.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26541.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26564.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26577.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26578.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26583.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26586.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26588.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26591.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26602.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26607.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26608.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26616.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26626.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26632.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26634.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26635.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26636.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26642.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26644.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26648.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26649.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26653.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26662.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26667.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26672.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26674.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26676.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26682.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26684.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26701.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26709.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26711.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26715.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26723.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26727.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26730.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26732.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26741.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26742.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26743.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26744.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26746.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26747.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26748.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26755.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26756.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26765.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26781.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26791.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26795.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26803.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26807.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26810.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26811.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26820.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26834.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26839.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26843.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26850.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26862.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26871.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26874.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26876.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26887.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26892.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26898.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26900.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26902.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26908.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26921.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26940.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26947.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26954.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26958.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26960.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26961.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26965.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26975.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26988.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26993.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26995.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27001.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27002.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27018.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27020.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27025.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27029.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27030.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27048.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27049.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27050.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27055.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27061.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27091.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27097.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27101.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27104.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27127.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27145.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27147.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27161.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27169.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27180.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27188.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27193.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27203.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27205.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27212.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27214.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27216.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27218.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27219.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27245.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27279.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27285.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27287.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27288.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27289.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27292.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27298.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27299.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27300.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27302.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27305.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27313.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27314.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27324.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27331.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27335.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27345.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27347.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27348.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27352.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27354.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27363.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27372.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27378.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27379.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27380.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27382.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27389.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27408.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27414.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27430.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27449.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27452.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27458.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27459.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27463.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27470.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27473.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27475.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27476.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27477.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27483.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27486.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27493.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27500.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27503.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27507.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27525.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27527.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27528.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27534.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27542.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27544.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27574.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27587.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27588.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27589.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27613.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27616.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27618.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27619.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27621.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27629.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27630.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27631.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27636.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27642.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27649.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27657.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27665.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27667.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27678.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27684.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27692.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27693.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27699.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27703.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27707.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27709.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27714.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27717.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27730.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27733.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27739.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27741.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27750.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27753.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27767.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27776.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27783.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27785.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27786.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27789.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27794.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27801.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27818.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27819.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27826.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27827.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27829.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27830.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27832.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27845.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27862.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27875.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27887.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27889.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27897.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27911.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27913.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27914.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27920.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27921.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27922.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27923.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27927.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27931.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27935.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27942.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27951.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27957.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27958.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27968.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27983.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27987.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28012.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28016.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28023.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28025.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28037.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28066.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28070.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28083.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28101.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28107.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28127.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28136.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28145.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28147.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28171.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28182.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28193.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28194.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28196.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28200.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28217.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28222.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28229.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28230.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28241.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28261.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28269.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28272.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28291.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28311.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28316.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28322.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28334.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28344.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28346.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28365.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28376.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28379.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28382.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28383.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28387.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28397.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28405.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28407.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28413.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28421.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28431.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28437.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28438.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28440.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28441.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28448.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28449.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28458.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28463.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28465.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28471.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28473.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28476.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28488.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28494.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28496.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28502.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28508.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28517.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28534.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28536.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28542.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28546.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28547.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28552.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28557.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28559.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28569.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28576.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28578.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28586.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28590.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28591.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28594.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28606.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28609.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28618.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28621.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28625.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28629.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28631.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28638.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28641.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28646.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28649.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28662.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28663.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28665.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28668.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28676.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28680.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28684.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28685.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28693.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28700.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28708.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28711.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28712.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28717.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28723.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28732.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28733.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28740.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28746.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28753.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28761.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28762.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28763.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28766.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28785.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28788.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28792.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28800.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28802.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28808.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28809.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28818.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28820.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28827.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28832.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28835.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28836.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28837.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28840.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28845.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28857.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28861.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28869.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28873.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28878.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28882.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28886.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28891.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28906.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28911.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28912.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28914.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28919.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28927.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28938.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28939.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28946.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28950.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28952.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28953.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28958.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28960.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28961.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28962.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28983.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28984.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28993.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28995.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29001.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29002.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29007.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29009.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29030.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29060.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29062.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29081.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29089.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29093.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29095.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29096.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29099.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29102.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29106.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29116.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29117.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29120.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29125.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29135.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29139.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29141.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29151.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29157.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29159.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29170.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29171.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29178.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29180.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29185.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29194.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29201.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29213.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29215.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29217.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29218.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29230.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29231.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29232.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29240.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29241.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29246.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29249.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29260.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29266.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29284.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29287.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29289.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29290.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29301.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29303.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29304.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29305.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29308.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29316.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29317.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29318.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29320.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29326.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29335.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29374.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29378.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29382.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29385.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29386.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29387.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29388.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29390.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29399.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29408.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29416.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29418.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29428.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29430.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29433.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29438.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29444.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29446.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29454.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29460.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29462.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29463.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29465.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29469.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29483.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29495.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29504.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29519.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29522.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29526.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29527.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29528.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29529.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29545.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29567.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29572.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29580.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29582.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29585.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29586.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29591.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29592.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29594.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29599.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29608.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29610.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29616.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29621.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29624.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29627.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29633.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29635.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29636.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29637.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29651.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29652.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29653.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29656.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29657.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29686.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29689.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29690.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29695.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29715.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29716.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29722.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29727.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29729.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29730.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29732.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29743.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29751.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29752.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29758.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29760.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29767.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29787.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29789.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29800.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29801.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29811.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29812.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29815.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29820.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29826.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29828.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29832.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29868.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29870.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29872.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29876.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29879.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29881.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29883.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29886.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29894.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29900.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29902.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29905.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29906.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29908.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29922.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29930.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29931.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29933.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29934.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29939.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29941.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29945.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29950.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29957.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29959.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29960.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29962.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29977.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29981.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29984.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29985.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29990.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29995.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30004.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30005.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30007.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30016.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30018.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30030.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30033.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30047.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30050.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30054.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30060.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30064.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30074.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30077.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30080.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30088.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30109.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30112.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30118.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30125.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30145.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30159.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30162.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30165.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30172.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30176.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30194.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30197.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30204.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30217.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30218.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30225.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30226.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30238.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30241.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30242.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30243.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30244.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30251.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30255.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30267.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30270.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30275.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30292.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30296.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30297.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30310.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30311.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30334.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30336.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30346.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30355.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30356.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30360.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30365.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30370.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30386.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30391.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30413.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30418.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30423.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30425.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30426.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30431.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30439.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30447.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30448.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30452.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30453.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30465.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30466.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30471.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30483.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30487.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30489.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30495.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30496.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30498.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30499.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30500.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30513.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30516.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30522.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30527.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30528.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30540.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30546.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30562.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30578.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30596.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30602.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30603.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30604.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30608.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30621.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30630.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30642.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30645.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30651.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30653.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30654.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30655.xdti_16f_9t_96_soffnqbcka01.xdti_soffnqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30664.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30668.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30676.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30690.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30696.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30701.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30708.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30709.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30710.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30720.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30725.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30731.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30739.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30745.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30754.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30763.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30769.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30777.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30785.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30787.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30790.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30793.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30796.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30802.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30813.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30822.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30823.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30831.xdti_16f_9t_96_soffqa10.xdti_soffqa10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30833.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst14.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst18.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst20.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst34.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst45.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst49.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst58.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst85.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst91.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst99.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst100.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst116.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst118.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst155.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst172.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst191.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst226.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst229.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst238.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst249.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst254.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst269.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst271.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst280.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst286.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst294.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst304.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst308.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst316.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst336.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst340.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst346.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst354.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst358.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst368.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst373.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst377.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst381.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst390.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst393.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst395.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst402.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst412.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst425.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst434.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst456.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst459.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst478.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst480.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst483.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst485.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst486.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst487.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst511.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst518.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst529.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst543.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst544.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst555.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst572.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst573.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst586.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst589.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst608.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst643.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst658.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst660.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst661.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst668.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst673.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst677.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst686.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst695.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst717.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst718.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst728.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst730.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst739.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst749.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst751.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst756.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst763.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst785.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst787.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst802.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst807.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst821.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst830.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst831.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst837.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst841.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst845.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst864.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst899.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst908.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst929.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst930.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst931.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst941.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst944.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst952.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst961.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst966.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst985.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst995.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1000.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1013.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1021.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1025.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1035.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1047.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1051.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1052.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1072.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1078.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1109.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1115.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1134.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1139.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1153.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1157.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1164.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1174.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1191.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1199.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1219.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1223.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1224.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1230.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1250.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1251.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1278.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1294.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1295.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1300.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1311.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1315.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1322.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1324.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1326.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1331.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1336.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1350.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1359.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1367.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1387.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1389.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1390.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1401.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1402.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1411.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1419.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1435.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1441.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1457.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1466.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1471.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1475.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1488.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1492.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1501.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1504.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1526.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1530.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1533.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1550.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1567.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1589.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1596.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1598.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1617.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1618.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1625.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1636.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1637.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1639.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1642.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1664.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1675.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1720.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1731.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1743.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1744.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1747.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1748.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1774.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1781.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1783.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1793.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1818.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1822.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1826.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1852.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1866.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1868.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1879.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1891.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1893.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1894.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1896.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1900.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1913.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1918.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1921.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1931.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1941.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1942.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1944.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1951.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1958.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1965.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1971.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1980.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1984.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2000.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2007.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2013.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2021.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2044.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2050.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2054.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2064.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2104.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2136.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2146.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2155.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2186.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2190.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2197.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2203.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2215.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2217.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2222.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2235.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2251.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2260.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2262.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2270.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2285.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2286.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2288.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2301.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2337.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2343.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2349.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2361.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2363.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2407.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2410.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2416.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2422.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2433.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2438.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2442.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2453.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2459.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2461.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2463.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2468.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2473.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2485.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2493.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2508.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2522.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2535.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2536.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2549.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2567.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2576.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2581.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2610.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2627.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2629.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2642.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2645.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2652.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2679.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2684.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2687.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2693.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2695.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2704.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2711.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2721.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2724.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2748.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2755.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2778.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2793.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2796.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2800.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2816.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2821.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2825.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2832.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2836.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2838.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2840.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2841.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2842.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2844.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2846.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2849.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2869.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2891.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2898.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2899.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2906.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2922.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2925.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2932.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2933.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2934.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2940.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2946.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2954.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2957.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2971.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2983.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2990.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3031.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3037.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3044.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3058.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3060.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3061.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3063.xdti_16f_9t_96_sosaffqa10dh.xdti_sosaffqa10 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3064.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3065.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3067.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3071.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3072.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3073.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3078.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3093.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3095.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3098.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3112.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3123.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3149.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3152.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3159.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3160.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3163.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3167.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3192.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3196.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3199.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3205.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3214.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3216.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3218.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3224.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3231.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3249.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3264.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3270.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3272.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3276.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3277.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3278.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3279.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3290.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3293.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3303.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3304.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3307.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3339.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3340.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3349.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3351.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3366.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3389.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3406.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3418.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3440.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3443.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3447.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3456.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3470.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3490.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3491.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3497.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3509.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3510.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3541.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3543.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3556.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3594.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3599.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3600.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3616.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3629.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3633.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3636.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3647.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3651.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3659.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3662.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3665.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3673.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3676.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3691.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3714.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3742.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3752.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3759.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3772.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3773.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3774.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3777.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3782.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3787.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3794.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3810.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3815.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3830.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3855.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3863.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3864.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3870.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3872.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3877.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3879.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3893.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3910.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3922.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3937.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3953.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3957.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3959.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3967.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3968.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3969.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3974.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3996.xdti_16f_9t_96_soffqa10.xdti_soffqa10 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4003.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4015.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4023.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4048.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4063.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4074.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4083.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4089.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4092.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4118.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4120.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4125.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4137.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4142.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4147.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4177.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4183.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4190.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4211.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4218.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4226.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4234.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4240.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4241.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4249.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4261.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4264.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4266.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4272.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4278.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4293.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4309.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4320.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4325.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4346.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4349.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4353.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4364.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4374.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4383.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4391.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4405.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4408.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4410.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4415.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4418.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4425.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4431.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4438.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4447.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4452.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4458.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4465.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4466.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4474.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4510.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4512.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4516.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4540.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4541.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4544.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4573.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4593.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4594.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4596.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4610.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4637.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4639.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4648.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4663.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4671.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4687.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4693.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4695.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4701.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4708.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4730.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4739.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4748.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4778.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4785.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4827.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4852.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4853.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4860.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4865.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4869.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4874.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4888.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4893.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4903.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4906.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4963.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4975.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4979.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4994.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5006.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5013.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5025.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5032.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5051.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5066.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5083.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5089.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5101.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5105.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5147.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5150.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5151.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5154.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5161.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5165.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5166.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5179.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5186.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5201.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5212.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5215.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5216.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5223.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5231.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5245.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5253.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5254.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5264.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5293.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5306.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5313.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5333.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5335.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5337.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5342.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5353.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5355.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5380.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5394.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5406.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5441.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5444.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5445.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5466.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5490.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5496.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5518.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5519.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5524.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5531.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5536.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5537.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5541.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5556.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5577.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5583.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5603.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5604.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5617.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5623.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5642.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5657.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5661.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5668.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5675.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5692.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5697.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5699.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5715.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5718.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5722.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5726.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5731.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5739.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5741.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5752.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5767.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5769.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5771.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5772.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5774.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5777.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5787.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5790.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5795.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5801.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5805.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5824.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5827.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5828.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5839.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5843.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5854.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5890.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5905.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5914.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5942.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5946.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5951.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5964.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5967.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5973.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6014.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6016.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6018.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6026.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6027.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6029.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6034.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6035.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6037.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6038.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6048.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6057.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6069.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6086.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6096.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6097.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6102.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6103.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6112.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6113.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6120.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6126.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6133.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6138.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6140.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6146.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6151.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6152.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6156.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6165.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6172.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6180.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6185.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6206.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6210.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6219.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6226.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6239.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6240.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6242.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6248.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6251.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6254.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6263.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6270.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6274.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6277.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6278.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6290.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6296.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6297.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6298.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6305.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6319.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6326.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6334.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6366.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6369.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6371.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6376.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6379.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6384.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6391.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6418.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6427.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6428.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6469.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6488.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6495.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6498.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6502.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6508.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6510.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6511.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6523.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6524.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6536.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6543.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6556.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6558.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6560.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6570.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6575.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6576.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6579.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6588.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6604.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6616.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6621.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6626.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6644.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6645.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6682.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6685.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6697.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6709.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6725.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6730.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6736.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6742.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6752.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6753.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6759.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6769.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6772.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6776.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6778.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6784.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6816.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6820.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6848.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6859.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6874.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6881.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6906.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6920.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6934.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6943.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6956.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6969.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6971.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6974.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6980.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7002.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7019.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7040.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7050.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7052.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7062.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7065.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7074.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7104.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7115.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7125.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7130.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7150.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7158.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7170.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7186.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7194.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7200.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7221.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7235.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7238.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7269.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7279.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7296.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7326.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7329.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7330.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7336.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7337.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7342.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7344.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7347.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7359.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7362.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7399.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7403.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7406.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7409.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7411.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7420.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7440.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7445.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7446.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7452.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7468.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7469.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7494.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7502.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7505.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7506.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7516.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7519.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7525.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7537.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7558.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7576.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7578.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7581.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7583.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7595.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7605.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7613.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7633.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7634.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7635.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7642.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7654.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7656.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7664.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7672.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7675.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7678.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7703.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7722.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7727.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7728.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7735.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7748.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7776.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7790.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7793.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7801.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7808.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7824.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7846.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7851.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7860.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7872.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7876.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7892.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7903.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7908.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7918.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7933.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7934.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7938.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7945.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7965.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7970.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7982.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7986.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8007.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8020.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8038.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8040.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8047.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8048.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8059.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8061.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8064.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8070.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8071.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8075.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8080.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8092.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8110.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8117.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8118.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8120.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8131.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8133.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8134.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8136.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8144.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8146.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8152.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8154.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8158.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8163.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8165.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8169.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8171.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8172.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8173.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8178.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8202.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8204.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8226.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8233.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8241.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8258.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8259.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8260.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8268.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8289.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8306.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8315.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8326.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8328.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8335.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8336.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8339.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8341.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8346.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8349.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8374.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8386.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8391.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8408.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8442.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8443.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8472.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8483.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8521.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8534.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8544.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8547.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8563.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8565.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8579.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8600.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8604.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8611.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8617.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8633.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8634.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8637.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8643.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8649.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8658.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8672.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8673.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8674.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8686.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8690.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8699.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8701.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8703.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8725.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8745.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8762.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8765.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8790.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8797.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8803.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8804.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8815.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8857.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8862.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8867.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8876.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8882.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8883.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8885.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8939.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8941.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8962.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8967.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8968.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8976.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8983.xdti_16f_9t_96_soffqa10.xdti_soffqa10 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9003.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9008.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9013.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9020.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9038.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9081.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9087.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9110.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9111.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9124.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9127.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9167.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9183.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9186.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9202.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9210.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9212.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9216.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9225.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9232.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9238.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9245.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9249.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9283.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9296.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9302.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9314.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9323.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9331.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9340.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9359.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9361.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9374.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9378.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9383.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9397.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9402.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9403.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9411.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9461.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9470.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9476.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9493.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9494.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9501.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9509.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9522.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9549.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9551.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9560.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9566.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9569.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9590.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9595.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9609.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9616.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9635.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9645.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9667.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9685.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9693.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9696.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9702.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9723.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9724.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9726.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9744.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9760.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9763.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9776.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9780.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9782.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9786.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9788.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9796.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9808.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9816.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9820.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9834.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9841.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9845.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9851.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9863.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9871.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9881.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9883.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9884.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9897.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9909.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9919.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9946.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9951.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9959.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9961.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9963.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9966.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9967.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9968.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9969.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9977.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9982.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9988.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9993.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10005.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10006.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10008.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10014.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10028.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10047.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10066.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10067.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10090.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10091.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10092.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10111.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10116.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10120.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10121.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10125.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10129.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10167.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10168.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10196.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10206.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10211.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10213.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10223.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10234.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10236.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10240.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10256.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10285.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10292.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10309.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10328.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10338.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10350.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10360.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10362.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10363.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10374.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10395.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10399.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10403.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10447.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10448.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10457.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10462.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10467.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10476.xdti_16f_9t_96_sosaffqa10dh.xdti_sosaffqa10 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10478.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10482.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10487.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10503.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10511.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10524.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10531.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10534.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10539.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10541.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10543.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10549.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10553.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10570.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10587.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10588.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10591.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10594.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10595.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10598.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10600.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10603.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10609.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10618.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10627.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10629.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10646.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10648.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10650.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10651.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10688.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10703.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10711.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10727.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10728.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10741.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10745.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10758.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10760.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10786.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10811.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10814.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10819.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10829.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10841.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10842.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10861.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10868.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10870.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10874.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10878.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10882.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10884.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10894.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10923.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10930.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10940.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10944.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10945.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10949.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10959.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10962.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10972.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10988.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11005.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11016.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11033.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11048.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11058.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11071.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11098.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11100.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11102.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11103.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11104.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11128.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11159.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11168.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11169.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11170.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11173.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11192.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11193.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11195.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11198.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11210.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11226.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11257.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11261.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11262.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11264.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11266.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11300.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11303.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11312.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11318.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11336.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11346.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11363.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11376.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11378.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11381.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11388.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11403.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11412.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11413.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11423.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11425.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11428.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11449.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11450.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11459.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11471.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11485.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11489.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11504.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11505.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11524.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11529.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11534.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11539.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11552.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11556.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11563.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11571.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11579.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11580.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11607.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11609.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11615.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11618.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11620.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11621.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11623.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11631.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11636.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11648.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11673.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11678.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11679.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11694.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11704.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11741.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11748.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11760.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11764.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11766.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11769.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11782.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11784.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11809.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11816.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11828.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11850.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11854.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11855.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11877.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11887.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11889.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11897.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11900.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11904.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11908.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11929.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11937.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11970.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11981.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11985.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11997.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12003.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12011.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12015.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12020.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12023.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12030.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12035.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12037.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12054.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12090.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12094.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12102.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12106.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12123.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12131.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12136.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12158.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12174.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12184.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12194.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12198.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12199.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12208.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12211.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12219.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12224.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12228.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12237.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12252.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12285.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12290.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12299.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12301.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12312.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12317.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12327.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12333.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12345.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12347.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12353.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12355.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12366.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12369.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12380.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12382.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12384.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12389.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12391.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12418.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12421.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12429.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12444.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12462.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12465.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12482.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12483.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12484.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12499.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12501.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12510.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12512.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12519.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12538.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12548.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12551.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12559.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12563.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12566.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12577.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12583.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12600.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12625.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12630.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12647.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12662.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12681.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12684.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12689.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12694.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12697.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12707.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12723.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12726.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12732.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12734.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12747.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12751.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12781.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12785.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12799.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12803.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12807.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12817.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12822.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12831.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12840.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12869.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12872.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12877.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12881.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12884.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12894.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12901.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12944.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12949.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12955.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12977.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12980.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12993.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13002.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13004.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13008.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13014.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13016.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13017.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13036.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13042.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13066.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13068.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13075.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13078.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13096.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13104.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13111.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13119.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13123.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13143.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13169.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13181.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13182.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13210.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13218.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13239.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13246.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13250.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13254.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13260.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13275.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13297.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13307.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13315.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13319.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13322.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst13323.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst14.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst18.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst20.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst34.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst45.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst49.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst58.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst85.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst91.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst99.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst100.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst116.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst118.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst155.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst172.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst191.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst226.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst229.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst238.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst249.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst254.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst269.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst271.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst280.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst286.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst294.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst304.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst308.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst316.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst336.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst340.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst346.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst354.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst358.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst368.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst373.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst377.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst381.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst390.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst393.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst395.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst402.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst412.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst425.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst434.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst456.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst459.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst478.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst480.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst483.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst485.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst486.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst487.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst511.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst518.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst529.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst543.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst544.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst555.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst572.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst573.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst586.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst589.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst608.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst643.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst658.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst660.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst661.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst668.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst673.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst677.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst686.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst695.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst717.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst718.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst728.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst730.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst739.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst749.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst751.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst756.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst763.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst785.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst787.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst802.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst807.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst821.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst830.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst831.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst837.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst841.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst845.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst864.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst899.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst908.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst929.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst930.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst931.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst941.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst944.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst952.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst961.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst966.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst985.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst995.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1000.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1013.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1021.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1025.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1035.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1047.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1051.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1052.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1072.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1078.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1109.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1115.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1134.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1139.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1153.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1157.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1164.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1174.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1191.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1199.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1219.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1223.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1224.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1230.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1250.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1251.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1278.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1294.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1295.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1300.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1311.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1315.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1322.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1324.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1326.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1331.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1336.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1350.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1359.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1367.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1387.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1389.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1390.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1401.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1402.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1411.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1419.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1435.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1441.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1457.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1466.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1471.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1475.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1488.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1492.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1501.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1504.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1526.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1530.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1533.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1550.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1567.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1589.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1596.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1598.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1617.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1618.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1625.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1636.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1637.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1639.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1642.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1664.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1675.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1720.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1731.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1743.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1744.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1747.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1748.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1774.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1781.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1783.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1793.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1818.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1822.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1826.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1852.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1866.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1868.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1879.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1891.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1893.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1894.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1896.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1900.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1913.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1918.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1921.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1931.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1941.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1942.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1944.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1951.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1958.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1965.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1971.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1980.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1984.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2000.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2007.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2013.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2021.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2044.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2050.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2054.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2064.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2104.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2136.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2146.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2155.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2186.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2190.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2197.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2203.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2215.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2217.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2222.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2235.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2251.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2260.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2262.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2270.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2285.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2286.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2288.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2301.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2337.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2343.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2349.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2361.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2363.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2407.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2410.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2416.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2422.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2433.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2438.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2442.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2453.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2459.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2461.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2463.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2468.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2473.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2485.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2493.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2508.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2522.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2535.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2536.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2549.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2567.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2576.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2581.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2610.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2627.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2629.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2642.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2645.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2652.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2679.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2684.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2687.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2693.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2695.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2704.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2711.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2721.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2724.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2748.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2755.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2778.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2793.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2796.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2800.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2816.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2821.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2825.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2832.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2836.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2838.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2840.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2841.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2842.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2844.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2846.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2849.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2869.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2891.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2898.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2899.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2906.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2922.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2925.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2932.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2933.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2934.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2940.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2946.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2954.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2957.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2971.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2983.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2990.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3031.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3037.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3044.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3058.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3060.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3061.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3063.xdti_16f_9t_96_sosaffqa10dh.xdti_sosaffqa10 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3064.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3065.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3067.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3071.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3072.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3073.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3078.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3093.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3095.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3098.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3112.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3123.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3149.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3152.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3159.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3160.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3163.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3167.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3192.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3196.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3199.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3205.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3214.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3216.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3218.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3224.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3231.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3249.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3264.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3270.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3272.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3276.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3277.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3278.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3279.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3290.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3293.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3303.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3304.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3307.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3339.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3340.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3349.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3351.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3366.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3389.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3406.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3418.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3440.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3443.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3447.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3456.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3470.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3490.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3491.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3497.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3509.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3510.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3541.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3543.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3556.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3594.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3599.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3600.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3616.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3629.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3633.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3636.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3647.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3651.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3659.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3662.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3665.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3673.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3676.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3691.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3714.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3742.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3752.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3759.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3772.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3773.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3774.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3777.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3782.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3787.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3794.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3810.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3815.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3830.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3855.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3863.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3864.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3870.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3872.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3877.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3879.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3893.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3910.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3922.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3937.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3953.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3957.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3959.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3967.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3968.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3969.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3974.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3996.xdti_16f_9t_96_soffqa10.xdti_soffqa10 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4003.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4015.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4023.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4048.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4063.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4074.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4083.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4089.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4092.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4118.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4120.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4125.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4137.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4142.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4147.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4177.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4183.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4190.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4211.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4218.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4226.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4234.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4240.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4241.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4249.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4261.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4264.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4266.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4272.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4278.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4293.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4309.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4320.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4325.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4346.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4349.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4353.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4364.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4374.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4383.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4391.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4405.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4408.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4410.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4415.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4418.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4425.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4431.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4438.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4447.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4452.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4458.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4465.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4466.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4474.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4510.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4512.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4516.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4540.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4541.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4544.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4573.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4593.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4594.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4596.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4610.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4637.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4639.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4648.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4663.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4671.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4687.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4693.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4695.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4701.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4708.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4730.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4739.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4748.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4778.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4785.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4827.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4852.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4853.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4860.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4865.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4869.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4874.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4888.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4893.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4903.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4906.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4963.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4975.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4979.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4994.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5006.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5013.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5025.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5032.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5051.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5066.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5083.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5089.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5101.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5105.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5147.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5150.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5151.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5154.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5161.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5165.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5166.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5179.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5186.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5201.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5212.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5215.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5216.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5223.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5231.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5245.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5253.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5254.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5264.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5293.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5306.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5313.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5333.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5335.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5337.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5342.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5353.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5355.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5380.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5394.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5406.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5441.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5444.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5445.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5466.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5490.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5496.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5518.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5519.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5524.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5531.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5536.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5537.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5541.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5556.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5577.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5583.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5603.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5604.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5617.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5623.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5642.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5657.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5661.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5668.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5675.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5692.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5697.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5699.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5715.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5718.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5722.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5726.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5731.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5739.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5741.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5752.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5767.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5769.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5771.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5772.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5774.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5777.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5787.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5790.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5795.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5801.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5805.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5824.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5827.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5828.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5839.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5843.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5854.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5890.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5905.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5914.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5942.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5946.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5951.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5964.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5967.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5973.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6014.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6016.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6018.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6026.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6027.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6029.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6034.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6035.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6037.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6038.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6048.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6057.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6069.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6086.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6096.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6097.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6102.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6103.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6112.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6113.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6120.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6126.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6133.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6138.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6140.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6146.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6151.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6152.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6156.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6165.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6172.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6180.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6185.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6206.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6210.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6219.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6226.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6239.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6240.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6242.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6248.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6251.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6254.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6263.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6270.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6274.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6277.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6278.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6290.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6296.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6297.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6298.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6305.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6319.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6326.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6334.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6366.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6369.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6371.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6376.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6379.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6384.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6391.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6418.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6427.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6428.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6469.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6488.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6495.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6498.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6502.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6508.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6510.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6511.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6523.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6524.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6536.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6543.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6556.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6558.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6560.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6570.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6575.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6576.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6579.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6588.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6604.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6616.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6621.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6626.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6644.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6645.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6682.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6685.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6697.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6709.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6725.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6730.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6736.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6742.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6752.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6753.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6759.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6769.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6772.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6776.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6778.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6784.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6816.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6820.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6848.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6859.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6874.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6881.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6906.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6920.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6934.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6943.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6956.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6969.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6971.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6974.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6980.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7002.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7019.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7040.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7050.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7052.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7062.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7065.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7074.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7104.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7115.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7125.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7130.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7150.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7158.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7170.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7186.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7194.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7200.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7221.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7235.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7238.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7269.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7279.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7296.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7326.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7329.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7330.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7336.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7337.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7342.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7344.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7347.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7359.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7362.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7399.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7403.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7406.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7409.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7411.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7420.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7440.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7445.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7446.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7452.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7468.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7469.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7494.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7502.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7505.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7506.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7516.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7519.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7525.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7537.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7558.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7576.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7578.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7581.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7583.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7595.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7605.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7613.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7633.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7634.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7635.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7642.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7654.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7656.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7664.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7672.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7675.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7678.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7703.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7722.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7727.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7728.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7735.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7748.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7776.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7790.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7793.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7801.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7808.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7824.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7846.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7851.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7860.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7872.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7876.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7892.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7903.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7908.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7918.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7933.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7934.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7938.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7945.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7965.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7970.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7982.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7986.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8007.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8020.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8038.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8040.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8047.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8048.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8059.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8061.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8064.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8070.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8071.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8075.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8080.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8092.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8110.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8117.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8118.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8120.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8131.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8133.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8134.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8136.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8144.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8146.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8152.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8154.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8158.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8163.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8165.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8169.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8171.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8172.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8173.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8178.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8202.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8204.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8226.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8233.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8241.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8258.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8259.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8260.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8268.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8289.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8306.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8315.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8326.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8328.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8335.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8336.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8339.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8341.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8346.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8349.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8374.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8386.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8391.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8408.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8442.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8443.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8472.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8483.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8521.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8534.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8544.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8547.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8563.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8565.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8579.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8600.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8604.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8611.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8617.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8633.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8634.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8637.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8643.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8649.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8658.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8672.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8673.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8674.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8686.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8690.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8699.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8701.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8703.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8725.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8745.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8762.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8765.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8790.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8797.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8803.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8804.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8815.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8857.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8862.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8867.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8876.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8882.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8883.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8885.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8939.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8941.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8962.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8967.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8968.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8976.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8983.xdti_16f_9t_96_soffqa10.xdti_soffqa10 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9003.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9008.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9013.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9020.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9038.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9081.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9087.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9110.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9111.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9124.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9127.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9167.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9183.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9186.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9202.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9210.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9212.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9216.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9225.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9232.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9238.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9245.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9249.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9283.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9296.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9302.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9314.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9323.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9331.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9340.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9359.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9361.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9374.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9378.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9383.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9397.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9402.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9403.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9411.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9461.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9470.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9476.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9493.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9494.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9501.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9509.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9522.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9549.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9551.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9560.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9566.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9569.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9590.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9595.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9609.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9616.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9635.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9645.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9667.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9685.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9693.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9696.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9702.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9723.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9724.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9726.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9744.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9760.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9763.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9776.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9780.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9782.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9786.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9788.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9796.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9808.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9816.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9820.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9834.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9841.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9845.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9851.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9863.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9871.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9881.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9883.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9884.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9897.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9909.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9919.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9946.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9951.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9959.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9961.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9963.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9966.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9967.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9968.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9969.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9977.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9982.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9988.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9993.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10005.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10006.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10008.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10014.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10028.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10047.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10066.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10067.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10090.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10091.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10092.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10111.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10116.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10120.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10121.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10125.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10129.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10167.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10168.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10196.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10206.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10211.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10213.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10223.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10234.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10236.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10240.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10256.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10285.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10292.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10309.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10328.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10338.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10350.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10360.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10362.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10363.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10374.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10395.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10399.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10403.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10447.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10448.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10457.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10462.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10467.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10476.xdti_16f_9t_96_sosaffqa10dh.xdti_sosaffqa10 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10478.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10482.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10487.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10503.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10511.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10524.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10531.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10534.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10539.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10541.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10543.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10549.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10553.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10570.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10587.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10588.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10591.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10594.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10595.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10598.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10600.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10603.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10609.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10618.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10627.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10629.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10646.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10648.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10650.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10651.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10688.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10703.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10711.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10727.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10728.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10741.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10745.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10758.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10760.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10786.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10811.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10814.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10819.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10829.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10841.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10842.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10861.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10868.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10870.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10874.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10878.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10882.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10884.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10894.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10923.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10930.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10940.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10944.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10945.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10949.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10959.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10962.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10972.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10988.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11005.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11016.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11033.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11048.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11058.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11071.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11098.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11100.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11102.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11103.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11104.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11128.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11159.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11168.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11169.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11170.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11173.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11192.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11193.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11195.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11198.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11210.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11226.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11257.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11261.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11262.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11264.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11266.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11300.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11303.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11312.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11318.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11336.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11346.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11363.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11376.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11378.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11381.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11388.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11403.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11412.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11413.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11423.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11425.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11428.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11449.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11450.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11459.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11471.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11485.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11489.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11504.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11505.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11524.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11529.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11534.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11539.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11552.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11556.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11563.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11571.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11579.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11580.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11607.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11609.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11615.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11618.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11620.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11621.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11623.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11631.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11636.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11648.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11673.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11678.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11679.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11694.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11704.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11741.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11748.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11760.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11764.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11766.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11769.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11782.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11784.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11809.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11816.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11828.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11850.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11854.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11855.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11877.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11887.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11889.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11897.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11900.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11904.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11908.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11929.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11937.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11970.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11981.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11985.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11997.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12003.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12011.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12015.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12020.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12023.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12030.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12035.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12037.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12054.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12090.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12094.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12102.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12106.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12123.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12131.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12136.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12158.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12174.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12184.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12194.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12198.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12199.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12208.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12211.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12219.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12224.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12228.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12237.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12252.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12285.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12290.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12299.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12301.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12312.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12317.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12327.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12333.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12345.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12347.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12353.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12355.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12366.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12369.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12380.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12382.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12384.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12389.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12391.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12418.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12421.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12429.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12444.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12462.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12465.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12482.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12483.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12484.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12499.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12501.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12510.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12512.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12519.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12538.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12548.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12551.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12559.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12563.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12566.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12577.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12583.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12600.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12625.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12630.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12647.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12662.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12681.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12684.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12689.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12694.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12697.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12707.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12723.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12726.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12732.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12734.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12747.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12751.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12781.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12785.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12799.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12803.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12807.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12817.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12822.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12831.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12840.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12869.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12872.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12877.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12881.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12884.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12894.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12901.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12944.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12949.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12955.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12977.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12980.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12993.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13002.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13004.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13008.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13014.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13016.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13017.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13036.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13042.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13066.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13068.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13075.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13078.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13096.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13104.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13111.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13119.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13123.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13143.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13169.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13181.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13182.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13210.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13218.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13239.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13246.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13250.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13254.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13260.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13275.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13297.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13307.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13315.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13319.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13322.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst13323.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst14.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst18.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst20.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst34.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst45.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst49.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst58.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst85.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst91.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst99.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst100.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst116.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst118.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst155.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst172.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst191.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst226.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst229.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst238.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst249.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst254.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst269.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst271.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst280.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst286.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst294.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst304.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst308.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst316.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst336.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst340.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst346.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst354.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst358.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst368.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst373.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst377.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst381.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst390.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst393.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst395.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst402.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst412.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst425.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst434.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst456.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst459.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst478.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst480.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst483.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst485.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst486.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst487.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst511.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst518.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst529.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst543.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst544.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst555.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst572.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst573.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst586.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst589.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst608.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst643.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst658.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst660.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst661.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst668.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst673.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst677.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst686.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst695.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst717.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst718.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst728.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst730.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst739.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst749.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst751.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst756.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst763.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst785.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst787.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst802.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst807.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst821.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst830.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst831.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst837.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst841.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst845.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst864.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst899.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst908.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst929.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst930.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst931.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst941.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst944.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst952.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst961.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst966.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst985.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst995.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1000.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1013.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1021.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1025.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1035.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1047.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1051.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1052.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1072.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1078.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1109.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1115.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1134.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1139.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1153.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1157.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1164.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1174.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1191.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1199.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1219.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1223.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1224.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1230.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1250.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1251.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1278.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1294.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1295.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1300.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1311.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1315.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1322.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1324.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1326.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1331.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1336.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1350.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1359.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1367.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1387.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1389.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1390.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1401.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1402.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1411.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1419.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1435.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1441.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1457.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1466.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1471.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1475.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1488.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1492.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1501.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1504.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1526.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1530.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1533.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1550.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1567.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1589.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1596.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1598.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1617.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1618.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1625.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1636.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1637.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1639.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1642.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1664.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1675.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1720.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1731.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1743.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1744.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1747.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1748.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1774.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1781.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1783.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1793.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1818.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1822.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1826.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1852.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1866.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1868.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1879.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1891.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1893.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1894.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1896.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1900.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1913.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1918.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1921.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1931.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1941.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1942.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1944.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1951.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1958.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1965.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1971.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1980.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1984.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2000.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2007.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2013.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2021.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2044.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2050.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2054.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2064.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2104.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2136.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2146.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2155.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2186.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2190.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2197.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2203.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2215.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2217.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2222.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2235.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2251.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2260.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2262.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2270.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2285.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2286.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2288.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2301.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2337.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2343.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2349.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2361.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2363.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2407.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2410.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2416.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2422.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2433.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2438.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2442.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2453.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2459.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2461.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2463.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2468.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2473.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2485.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2493.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2508.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2522.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2535.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2536.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2549.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2567.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2576.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2581.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2610.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2627.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2629.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2642.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2645.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2652.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2679.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2684.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2687.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2693.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2695.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2704.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2711.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2721.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2724.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2748.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2755.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2778.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2793.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2796.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2800.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2816.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2821.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2825.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2832.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2836.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2838.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2840.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2841.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2842.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2844.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2846.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2849.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2869.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2891.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2898.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2899.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2906.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2922.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2925.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2932.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2933.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2934.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2940.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2946.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2954.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2957.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2971.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2983.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2990.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3031.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3037.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3044.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3058.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3060.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3061.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3063.xdti_16f_9t_96_sosaffqa10dh.xdti_sosaffqa10 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3064.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3065.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3067.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3071.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3072.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3073.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3078.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3093.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3095.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3098.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3112.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3123.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3149.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3152.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3159.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3160.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3163.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3167.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3192.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3196.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3199.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3205.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3214.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3216.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3218.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3224.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3231.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3249.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3264.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3270.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3272.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3276.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3277.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3278.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3279.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3290.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3293.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3303.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3304.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3307.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3339.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3340.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3349.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3351.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3366.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3389.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3406.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3418.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3440.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3443.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3447.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3456.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3470.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3490.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3491.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3497.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3509.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3510.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3541.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3543.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3556.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3594.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3599.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3600.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3616.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3629.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3633.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3636.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3647.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3651.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3659.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3662.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3665.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3673.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3676.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3691.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3714.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3742.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3752.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3759.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3772.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3773.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3774.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3777.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3782.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3787.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3794.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3810.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3815.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3830.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3855.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3863.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3864.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3870.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3872.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3877.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3879.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3893.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3910.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3922.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3937.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3953.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3957.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3959.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3967.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3968.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3969.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3974.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3996.xdti_16f_9t_96_soffqa10.xdti_soffqa10 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4003.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4015.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4023.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4048.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4063.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4074.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4083.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4089.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4092.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4118.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4120.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4125.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4137.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4142.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4147.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4177.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4183.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4190.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4211.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4218.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4226.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4234.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4240.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4241.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4249.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4261.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4264.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4266.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4272.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4278.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4293.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4309.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4320.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4325.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4346.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4349.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4353.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4364.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4374.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4383.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4391.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4405.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4408.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4410.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4415.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4418.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4425.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4431.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4438.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4447.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4452.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4458.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4465.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4466.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4474.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4510.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4512.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4516.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4540.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4541.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4544.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4573.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4593.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4594.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4596.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4610.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4637.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4639.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4648.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4663.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4671.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4687.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4693.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4695.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4701.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4708.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4730.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4739.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4748.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4778.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4785.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4827.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4852.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4853.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4860.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4865.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4869.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4874.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4888.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4893.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4903.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4906.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4963.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4975.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4979.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4994.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5006.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5013.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5025.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5032.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5051.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5066.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5083.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5089.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5101.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5105.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5147.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5150.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5151.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5154.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5161.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5165.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5166.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5179.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5186.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5201.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5212.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5215.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5216.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5223.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5231.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5245.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5253.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5254.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5264.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5293.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5306.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5313.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5333.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5335.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5337.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5342.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5353.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5355.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5380.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5394.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5406.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5441.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5444.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5445.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5466.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5490.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5496.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5518.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5519.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5524.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5531.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5536.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5537.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5541.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5556.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5577.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5583.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5603.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5604.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5617.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5623.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5642.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5657.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5661.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5668.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5675.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5692.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5697.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5699.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5715.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5718.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5722.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5726.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5731.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5739.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5741.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5752.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5767.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5769.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5771.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5772.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5774.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5777.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5787.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5790.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5795.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5801.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5805.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5824.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5827.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5828.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5839.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5843.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5854.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5890.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5905.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5914.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5942.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5946.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5951.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5964.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5967.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5973.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6014.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6016.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6018.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6026.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6027.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6029.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6034.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6035.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6037.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6038.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6048.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6057.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6069.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6086.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6096.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6097.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6102.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6103.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6112.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6113.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6120.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6126.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6133.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6138.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6140.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6146.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6151.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6152.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6156.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6165.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6172.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6180.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6185.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6206.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6210.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6219.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6226.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6239.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6240.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6242.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6248.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6251.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6254.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6263.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6270.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6274.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6277.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6278.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6290.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6296.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6297.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6298.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6305.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6319.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6326.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6334.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6366.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6369.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6371.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6376.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6379.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6384.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6391.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6418.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6427.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6428.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6469.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6488.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6495.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6498.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6502.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6508.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6510.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6511.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6523.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6524.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6536.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6543.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6556.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6558.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6560.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6570.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6575.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6576.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6579.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6588.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6604.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6616.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6621.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6626.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6644.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6645.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6682.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6685.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6697.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6709.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6725.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6730.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6736.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6742.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6752.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6753.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6759.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6769.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6772.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6776.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6778.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6784.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6816.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6820.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6848.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6859.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6874.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6881.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6906.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6920.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6934.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6943.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6956.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6969.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6971.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6974.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6980.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7002.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7019.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7040.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7050.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7052.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7062.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7065.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7074.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7104.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7115.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7125.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7130.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7150.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7158.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7170.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7186.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7194.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7200.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7221.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7235.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7238.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7269.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7279.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7296.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7326.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7329.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7330.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7336.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7337.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7342.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7344.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7347.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7359.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7362.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7399.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7403.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7406.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7409.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7411.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7420.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7440.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7445.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7446.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7452.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7468.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7469.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7494.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7502.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7505.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7506.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7516.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7519.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7525.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7537.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7558.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7576.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7578.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7581.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7583.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7595.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7605.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7613.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7633.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7634.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7635.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7642.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7654.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7656.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7664.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7672.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7675.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7678.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7703.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7722.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7727.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7728.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7735.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7748.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7776.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7790.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7793.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7801.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7808.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7824.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7846.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7851.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7860.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7872.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7876.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7892.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7903.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7908.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7918.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7933.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7934.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7938.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7945.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7965.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7970.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7982.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7986.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8007.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8020.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8038.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8040.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8047.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8048.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8059.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8061.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8064.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8070.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8071.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8075.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8080.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8092.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8110.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8117.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8118.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8120.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8131.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8133.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8134.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8136.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8144.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8146.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8152.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8154.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8158.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8163.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8165.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8169.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8171.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8172.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8173.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8178.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8202.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8204.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8226.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8233.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8241.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8258.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8259.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8260.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8268.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8289.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8306.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8315.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8326.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8328.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8335.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8336.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8339.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8341.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8346.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8349.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8374.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8386.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8391.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8408.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8442.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8443.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8472.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8483.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8521.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8534.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8544.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8547.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8563.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8565.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8579.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8600.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8604.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8611.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8617.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8633.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8634.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8637.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8643.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8649.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8658.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8672.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8673.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8674.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8686.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8690.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8699.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8701.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8703.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8725.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8745.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8762.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8765.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8790.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8797.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8803.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8804.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8815.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8857.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8862.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8867.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8876.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8882.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8883.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8885.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8939.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8941.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8962.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8967.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8968.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8976.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8983.xdti_16f_9t_96_soffqa10.xdti_soffqa10 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9003.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9008.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9013.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9020.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9038.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9081.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9087.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9110.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9111.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9124.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9127.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9167.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9183.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9186.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9202.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9210.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9212.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9216.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9225.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9232.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9238.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9245.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9249.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9283.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9296.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9302.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9314.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9323.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9331.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9340.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9359.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9361.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9374.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9378.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9383.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9397.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9402.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9403.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9411.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9461.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9470.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9476.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9493.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9494.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9501.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9509.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9522.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9549.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9551.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9560.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9566.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9569.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9590.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9595.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9609.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9616.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9635.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9645.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9667.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9685.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9693.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9696.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9702.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9723.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9724.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9726.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9744.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9760.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9763.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9776.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9780.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9782.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9786.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9788.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9796.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9808.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9816.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9820.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9834.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9841.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9845.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9851.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9863.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9871.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9881.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9883.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9884.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9897.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9909.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9919.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9946.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9951.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9959.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9961.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9963.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9966.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9967.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9968.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9969.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9977.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9982.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9988.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9993.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10005.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10006.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10008.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10014.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10028.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10047.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10066.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10067.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10090.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10091.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10092.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10111.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10116.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10120.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10121.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10125.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10129.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10167.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10168.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10196.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10206.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10211.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10213.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10223.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10234.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10236.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10240.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10256.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10285.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10292.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10309.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10328.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10338.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10350.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10360.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10362.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10363.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10374.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10395.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10399.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10403.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10447.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10448.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10457.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10462.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10467.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10476.xdti_16f_9t_96_sosaffqa10dh.xdti_sosaffqa10 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10478.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10482.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10487.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10503.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10511.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10524.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10531.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10534.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10539.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10541.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10543.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10549.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10553.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10570.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10587.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10588.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10591.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10594.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10595.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10598.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10600.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10603.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10609.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10618.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10627.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10629.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10646.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10648.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10650.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10651.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10688.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10703.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10711.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10727.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10728.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10741.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10745.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10758.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10760.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10786.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10811.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10814.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10819.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10829.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10841.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10842.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10861.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10868.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10870.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10874.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10878.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10882.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10884.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10894.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10923.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10930.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10940.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10944.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10945.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10949.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10959.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10962.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10972.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10988.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11005.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11016.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11033.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11048.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11058.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11071.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11098.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11100.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11102.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11103.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11104.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11128.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11159.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11168.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11169.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11170.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11173.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11192.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11193.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11195.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11198.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11210.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11226.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11257.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11261.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11262.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11264.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11266.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11300.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11303.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11312.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11318.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11336.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11346.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11363.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11376.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11378.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11381.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11388.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11403.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11412.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11413.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11423.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11425.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11428.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11449.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11450.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11459.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11471.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11485.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11489.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11504.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11505.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11524.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11529.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11534.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11539.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11552.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11556.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11563.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11571.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11579.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11580.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11607.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11609.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11615.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11618.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11620.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11621.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11623.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11631.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11636.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11648.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11673.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11678.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11679.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11694.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11704.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11741.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11748.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11760.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11764.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11766.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11769.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11782.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11784.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11809.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11816.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11828.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11850.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11854.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11855.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11877.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11887.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11889.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11897.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11900.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11904.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11908.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11929.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11937.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11970.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11981.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11985.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11997.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12003.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12011.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12015.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12020.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12023.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12030.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12035.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12037.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12054.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12090.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12094.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12102.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12106.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12123.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12131.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12136.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12158.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12174.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12184.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12194.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12198.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12199.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12208.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12211.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12219.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12224.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12228.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12237.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12252.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12285.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12290.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12299.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12301.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12312.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12317.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12327.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12333.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12345.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12347.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12353.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12355.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12366.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12369.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12380.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12382.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12384.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12389.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12391.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12418.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12421.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12429.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12444.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12462.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12465.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12482.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12483.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12484.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12499.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12501.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12510.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12512.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12519.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12538.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12548.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12551.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12559.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12563.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12566.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12577.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12583.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12600.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12625.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12630.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12647.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12662.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12681.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12684.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12689.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12694.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12697.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12707.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12723.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12726.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12732.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12734.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12747.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12751.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12781.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12785.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12799.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12803.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12807.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12817.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12822.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12831.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12840.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12869.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12872.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12877.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12881.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12884.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12894.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12901.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12944.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12949.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12955.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12977.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12980.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12993.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13002.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13004.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13008.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13014.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13016.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13017.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13036.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13042.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13066.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13068.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13075.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13078.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13096.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13104.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13111.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13119.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13123.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13143.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13169.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13181.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13182.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13210.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13218.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13239.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13246.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13250.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13254.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13260.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13275.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13297.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13307.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13315.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13319.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13322.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst13323.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst14.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst18.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst20.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst34.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst45.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst49.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst58.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst85.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst91.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst99.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst100.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst116.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst118.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst155.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst172.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst191.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst226.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst229.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst238.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst249.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst254.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst269.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst271.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst280.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst286.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst294.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst304.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst308.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst316.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst336.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst340.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst346.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst354.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst358.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst368.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst373.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst377.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst381.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst390.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst393.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst395.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst402.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst412.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst425.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst434.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst456.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst459.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst478.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst480.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst483.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst485.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst486.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst487.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst511.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst518.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst529.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst543.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst544.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst555.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst572.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst573.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst586.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst589.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst608.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst643.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst658.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst660.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst661.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst668.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst673.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst677.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst686.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst695.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst717.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst718.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst728.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst730.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst739.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst749.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst751.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst756.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst763.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst785.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst787.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst802.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst807.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst821.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst830.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst831.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst837.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst841.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst845.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst864.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst899.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst908.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst929.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst930.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst931.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst941.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst944.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst952.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst961.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst966.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst985.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst995.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1000.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1013.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1021.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1025.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1035.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1047.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1051.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1052.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1072.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1078.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1109.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1115.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1134.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1139.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1153.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1157.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1164.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1174.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1191.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1199.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1219.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1223.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1224.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1230.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1250.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1251.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1278.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1294.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1295.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1300.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1311.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1315.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1322.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1324.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1326.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1331.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1336.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1350.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1359.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1367.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1387.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1389.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1390.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1401.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1402.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1411.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1419.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1435.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1441.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1457.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1466.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1471.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1475.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1488.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1492.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1501.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1504.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1526.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1530.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1533.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1550.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1567.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1589.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1596.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1598.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1617.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1618.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1625.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1636.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1637.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1639.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1642.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1664.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1675.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1720.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1731.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1743.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1744.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1747.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1748.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1774.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1781.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1783.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1793.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1818.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1822.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1826.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1829.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1852.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1866.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1868.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1879.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1891.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1893.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1894.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1896.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1900.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1913.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1918.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1921.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1931.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1941.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1942.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1944.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1951.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1958.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1965.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1971.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1980.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1984.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2000.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2007.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2013.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2021.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2044.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2050.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2054.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2064.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2104.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2136.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2146.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2155.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2186.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2190.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2197.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2203.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2215.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2217.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2222.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2235.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2251.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2260.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2262.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2270.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2285.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2286.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2288.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2301.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2337.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2343.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2349.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2356.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2361.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2363.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2372.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2404.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2407.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2410.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2416.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2422.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2433.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2438.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2442.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2453.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2459.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2461.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2463.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2468.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2473.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2485.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2493.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2508.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2522.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2535.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2536.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2549.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2567.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2576.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2581.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2610.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2627.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2629.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2642.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2645.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2652.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2679.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2684.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2687.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2693.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2695.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2704.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2711.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2721.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2724.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2748.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2755.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2778.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2793.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2796.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2800.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2816.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2821.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2825.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2832.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2836.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2838.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2839.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2840.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2841.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2842.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2844.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2846.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2849.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2869.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2891.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2898.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2899.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2906.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2922.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2925.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2932.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2933.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2934.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2940.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2943.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2946.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2954.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2957.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2971.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2983.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2990.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3031.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3037.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3044.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3058.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3060.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3061.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3063.xdti_16f_9t_96_sosaffqa10dh.xdti_sosaffqa10 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3064.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3065.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3067.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3071.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3072.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3073.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3078.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3093.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3095.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3098.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3112.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3123.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3149.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3152.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3159.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3160.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3163.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3167.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3192.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3196.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3199.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3205.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3214.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3216.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3218.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3224.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3231.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3249.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3264.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3270.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3272.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3276.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3277.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3278.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3279.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3290.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3293.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3303.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3304.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3307.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3339.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3340.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3349.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3351.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3366.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3389.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3406.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3418.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3440.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3443.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3447.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3456.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3470.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3490.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3491.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3497.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3509.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3510.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3541.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3543.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3556.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3594.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3599.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3600.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3616.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3629.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3633.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3636.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3647.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3651.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3659.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3662.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3665.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3673.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3676.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3691.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3709.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3714.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3742.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3752.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3759.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3772.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3773.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3774.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3777.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3779.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3782.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3787.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3794.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3810.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3815.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3830.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3855.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3863.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3864.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3870.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3872.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3877.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3879.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3893.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3910.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3922.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3937.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3953.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3957.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3959.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3967.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3968.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3969.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3974.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3996.xdti_16f_9t_96_soffqa10.xdti_soffqa10 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4003.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4010.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4015.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4023.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4048.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4063.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4074.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4083.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4089.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4092.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4118.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4120.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4125.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4137.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4142.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4147.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4177.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4183.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4190.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4211.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4218.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4226.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4234.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4240.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4241.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4244.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4249.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4261.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4264.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4266.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4272.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4278.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4293.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4309.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4320.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4325.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4346.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4349.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4353.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4364.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4374.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4383.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4391.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4405.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4408.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4410.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4415.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4418.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4425.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4431.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4438.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4447.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4452.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4458.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4465.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4466.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4474.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4510.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4512.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4516.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4540.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4541.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4544.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4573.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4593.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4594.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4596.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4610.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4637.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4639.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4648.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4663.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4671.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4687.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4693.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4695.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4701.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4708.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4730.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4739.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4748.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4778.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4785.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4827.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4852.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4853.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4860.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4865.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4869.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4874.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4888.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4893.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4903.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4906.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4963.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4975.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4979.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4994.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5006.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5013.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5025.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5027.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5032.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5051.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5066.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5083.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5089.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5101.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5105.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5121.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5124.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5147.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5150.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5151.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5154.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5161.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5165.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5166.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5179.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5186.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5201.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5212.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5215.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5216.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5220.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5223.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5231.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5245.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5253.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5254.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5264.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5276.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5293.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5306.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5313.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5333.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5335.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5337.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5342.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5353.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5355.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5380.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5394.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5406.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5424.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5427.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5441.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5444.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5445.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5466.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5490.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5496.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5518.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5519.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5524.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5531.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5536.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5537.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5541.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5556.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5577.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5583.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5603.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5604.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5617.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5623.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5642.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5657.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5661.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5668.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5675.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5692.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5697.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5699.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5715.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5718.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5722.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5726.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5731.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5739.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5741.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5752.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5764.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5767.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5769.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5771.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5772.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5774.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5777.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5787.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5790.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5795.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5801.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5804.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5805.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5811.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5824.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5827.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5828.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5839.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5843.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5854.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5890.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5905.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5914.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5942.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5946.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5951.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5964.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5967.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5973.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6014.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6016.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6018.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6026.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6027.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6029.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6032.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6034.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6035.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6037.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6038.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6041.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6046.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6048.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6057.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6069.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6086.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6096.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6097.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6102.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6103.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6112.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6113.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6120.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6126.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6129.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6133.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6138.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6140.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6146.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6151.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6152.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6156.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6157.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6165.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6172.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6180.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6185.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6206.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6210.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6219.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6226.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6239.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6240.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6242.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6248.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6251.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6254.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6256.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6263.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6270.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6274.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6277.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6278.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6290.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6296.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6297.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6298.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6301.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6305.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6306.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6319.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6325.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6326.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6327.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6334.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6366.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6369.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6371.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6376.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6379.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6384.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6391.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6418.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6427.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6428.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6437.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6469.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6488.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6495.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6498.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6502.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6508.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6510.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6511.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6523.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6524.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6536.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6543.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6554.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6556.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6558.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6560.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6570.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6575.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6576.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6579.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6588.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6604.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6616.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6621.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6626.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6644.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6645.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6682.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6685.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6697.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6709.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6725.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6730.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6736.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6738.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6742.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6752.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6753.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6759.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6769.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6772.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6776.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6778.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6783.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6784.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6816.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6820.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6848.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6859.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6874.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6881.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6906.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6920.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6934.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6943.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6956.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6969.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6971.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6974.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6980.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7002.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7019.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7040.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7050.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7052.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7062.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7065.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7074.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7104.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7115.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7125.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7130.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7150.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7158.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7170.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7175.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7186.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7194.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7200.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7212.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7221.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7235.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7238.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7258.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7269.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7279.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7296.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7326.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7329.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7330.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7336.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7337.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7342.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7344.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7347.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7359.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7362.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7399.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7403.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7406.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7409.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7411.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7420.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7440.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7443.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7445.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7446.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7452.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7468.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7469.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7494.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7502.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7505.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7506.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7516.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7519.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7525.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7537.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7558.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7576.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7578.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7581.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7583.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7595.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7605.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7613.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7633.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7634.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7635.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7642.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7646.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7654.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7656.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7664.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7666.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7672.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7675.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7678.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7703.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7721.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7722.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7727.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7728.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7735.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7748.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7764.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7776.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7790.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7793.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7798.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7801.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7808.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7824.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7846.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7847.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7851.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7860.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7872.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7876.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7889.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7892.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7903.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7908.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7918.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7933.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7934.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7938.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7945.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7965.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7970.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7982.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7986.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8007.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8020.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8036.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8038.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8040.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8042.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8047.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8048.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8059.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8061.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8064.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8070.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8071.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8075.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8080.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8092.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8110.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8117.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8118.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8120.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8131.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8133.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8134.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8136.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8144.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8146.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8152.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8154.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8158.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8163.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8165.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8169.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8171.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8172.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8173.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8178.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8202.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8204.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8226.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8233.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8241.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8255.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8258.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8259.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8260.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8268.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8281.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8289.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8306.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8315.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8316.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8321.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8326.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8328.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8335.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8336.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8339.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8341.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8346.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8349.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8374.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8386.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8391.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8397.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8408.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8442.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8443.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8472.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8483.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8521.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8532.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8534.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8544.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8547.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8563.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8565.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8579.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8600.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8604.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8611.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8617.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8632.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8633.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8634.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8637.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8643.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8649.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8658.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8672.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8673.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8674.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8686.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8690.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8699.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8701.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8703.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8725.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8733.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8745.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8762.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8765.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8790.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8797.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8803.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8804.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8815.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8831.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8853.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8857.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8862.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8867.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8876.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8882.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8883.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8884.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8885.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8921.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8939.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8941.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8962.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8967.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8968.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8976.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8978.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8983.xdti_16f_9t_96_soffqa10.xdti_soffqa10 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9003.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9008.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9013.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9020.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9038.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9045.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9081.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9087.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9110.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9111.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9124.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9127.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9146.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9167.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9183.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9186.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9202.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9210.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9212.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9216.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9225.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9232.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9238.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9245.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9249.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9273.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9283.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9291.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9295.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9296.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9302.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9314.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9321.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9323.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9331.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9340.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9359.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9361.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9367.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9374.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9378.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9383.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9392.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9397.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9399.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9402.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9403.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9407.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9411.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9422.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9461.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9469.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9470.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9476.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9493.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9494.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9500.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9501.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9509.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9522.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9549.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9551.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9560.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9566.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9569.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9590.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9595.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9602.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9607.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9609.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9616.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9623.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9635.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9645.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9667.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9685.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9689.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9693.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9696.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9702.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9706.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9723.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9724.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9726.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9744.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9760.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9763.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9775.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9776.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9780.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9782.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9786.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9788.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9796.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9808.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9816.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9820.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9834.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9841.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9845.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9851.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9863.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9871.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9881.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9883.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9884.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9897.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9909.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9912.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9919.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9946.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9948.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9951.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9959.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9961.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9963.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9966.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9967.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9968.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9969.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9977.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9982.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9988.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9993.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10005.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10006.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10008.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10014.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10022.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10028.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10047.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10066.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10067.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10090.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10091.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10092.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10111.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10114.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10116.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10120.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10121.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10125.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10129.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10162.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10167.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10168.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10184.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10195.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10196.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10206.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10211.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10213.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10223.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10234.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10236.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10240.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10256.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10268.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10282.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10285.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10292.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10309.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10328.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10338.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10345.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10350.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10360.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10362.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10363.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10374.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10395.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10396.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10399.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10403.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10447.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10448.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10457.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10462.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10467.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10476.xdti_16f_9t_96_sosaffqa10dh.xdti_sosaffqa10 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10478.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10482.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10487.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10503.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10511.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10514.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10517.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10524.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10531.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10534.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10539.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10541.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10542.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10543.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10549.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10553.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10560.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10565.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10570.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10587.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10588.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10591.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10594.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10595.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10598.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10600.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10603.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10609.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10612.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10618.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10627.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10628.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10629.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10646.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10648.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10650.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10651.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10688.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10703.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10711.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10727.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10728.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10735.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10741.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10743.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10745.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10757.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10758.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10760.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10768.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10786.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10795.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10811.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10814.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10815.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10819.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10829.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10841.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10842.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10861.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10868.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10870.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10874.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10878.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10882.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10884.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10894.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10898.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10916.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10923.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10930.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10940.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10944.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10945.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10949.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10952.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10955.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10959.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10962.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10972.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10988.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11005.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11016.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11026.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11033.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11048.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11058.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11071.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11098.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11100.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11102.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11103.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11104.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11128.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11159.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11168.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11169.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11170.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11173.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11192.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11193.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11195.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11198.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11207.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11210.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11226.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11246.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11257.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11261.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11262.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11264.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11266.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11300.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11303.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11308.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11312.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11318.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11336.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11338.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11346.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11357.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11363.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11370.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11371.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11376.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11378.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11381.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11388.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11403.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11412.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11413.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11423.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11425.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11428.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11449.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11450.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11459.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11471.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11481.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11484.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11485.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11489.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11504.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11505.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11506.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11515.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11518.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11524.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11526.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11529.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11534.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11539.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11552.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11556.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11563.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11571.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11579.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11580.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11607.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11609.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11615.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11618.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11619.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11620.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11621.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11623.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11631.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11636.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11648.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11665.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11673.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11678.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11679.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11686.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11694.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11698.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11704.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11711.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11741.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11748.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11760.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11764.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11766.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11769.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11782.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11784.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11809.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11816.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11828.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11850.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11854.xdti_16f_9t_96_soffqbcka01fo.xdti_soffqbcka01fo 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11855.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11856.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11859.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11877.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11887.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11888.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11889.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11897.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11900.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11904.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11908.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11929.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11936.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11937.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11970.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11973.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11981.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11985.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11997.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12003.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12011.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12015.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12020.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12023.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12030.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12035.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12037.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12054.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12062.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12069.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12085.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12090.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12093.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12094.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12099.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12102.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12106.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12119.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12123.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12130.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12131.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12134.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12136.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12150.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12158.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12174.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12183.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12184.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12191.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12194.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12198.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12199.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12208.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12211.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12219.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12224.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12228.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12237.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12252.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12285.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12290.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12299.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12301.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12309.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12312.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12313.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12317.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12327.xdti_16f_9t_96_soffqa10.xdti_soffqa10 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12332.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12333.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12345.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12347.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12353.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12355.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12366.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12369.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12380.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12381.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12382.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12384.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12389.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12391.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12417.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12418.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12421.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12429.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12434.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12436.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12444.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12462.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12465.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12482.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12483.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12484.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12488.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12499.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12501.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12510.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12512.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12519.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12535.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12538.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12544.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12548.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12550.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12551.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12553.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12559.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12563.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12566.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12577.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12582.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12583.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12585.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12600.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12624.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12625.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12626.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12630.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12641.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12647.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12662.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12669.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12681.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12684.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12689.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12694.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12697.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12707.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12723.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12726.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12729.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12732.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12734.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12747.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12751.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12781.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12785.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12799.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12803.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12805.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12807.xdti_16f_9t_96_soffqa10.xdti_soffqa10 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12817.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12822.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12831.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12840.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12869.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12872.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12877.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12881.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12884.xdti_16f_9t_96_soffqbckena10.xdti_soffqbckena10 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12894.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12901.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12944.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12949.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12955.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12969.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12977.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12980.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12987.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12993.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12999.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13002.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13004.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13008.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13009.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13014.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13016.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13017.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13023.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13033.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 16.67 16.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13036.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13042.flop.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13043.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13053.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13066.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13068.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13075.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13078.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13079.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13080.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 29.17 29.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13096.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 4.17 4.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13104.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13107.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13108.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13111.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13113.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 58.33 58.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13119.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 54.17 54.17
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13123.xdti_16f_9t_96_sosaffqa01dh.xdti_sosaffqa01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13140.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13143.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13169.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13181.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13182.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13208.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13210.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 25.00 25.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13218.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 41.67 41.67
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13239.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13243.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13246.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13250.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13254.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13260.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 37.50 37.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13275.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13284.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13297.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13307.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 33.33 33.33
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13315.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 20.83 20.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13317.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13319.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13320.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 45.83 45.83
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13322.xdti_16f_9t_96_soffqbcka01.xdti_soffqbcka01 12.50 12.50
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst13323.xdti_16f_9t_96_soffqbckena01.xdti_soffqbckena01 12.50 12.50

Toggle Coverage for Module : dti_flop_asyn_soffa_top
TotalCoveredPercent
Totals 12 8 66.67
Total Bits 24 16 66.67
Total Bits 0->1 12 8 66.67
Total Bits 1->0 12 8 66.67

Ports 12 8 66.67
Port Bits 24 16 66.67
Port Bits 0->1 12 8 66.67
Port Bits 1->0 12 8 66.67

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
VDD No No No INPUT
VSS No No No INPUT
Q Yes Yes Yes OUTPUT
SO Yes Yes Yes OUTPUT
CK Yes Yes Yes INPUT
D Yes Yes Yes INPUT
SD Yes Yes Yes INPUT
SE No No No INPUT
RN Yes Yes Yes INPUT
CE Yes Yes Yes INPUT
SN Yes Yes Yes INPUT
notifier No No No INPUT

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